STM b_u585i_iot02a NOR flash and OSPI_SPI_MODE, erase failed

[JiiZR]

Describe the bug Running twice samples/drivers/spi_flash test with altered data, test fails.

It seems that flash erase is failing. When using OPI mode ja DTR speed everything is OK.

To Reproduce Steps to reproduce the behavior:

1. modify \zephyr\boards\arm\b_u585i_iot02a\b_u585i_iot02a-common.dtsi

   mx25lm51245: ospi-nor-flash@0 { ... spi-bus-width = ; data-rate = ;

2. west build -p auto -b b_u585i_iot02a_ns samples/drivers/spi_flash

3. west flash

4. See prints: Booting Zephyr OS build zephyr-v3.1.0-3616-g5af932f6e788

ospi-nor-flash@0 SPI flash testing

Test 1: Flash erase Flash erase succeeded!

Test 2: Flash write Attempting to write 4 bytes Data read matches data written. Good!!

5. modify \zephyr\samples\drivers\spi_flash\src\main.c const uint8_t expected[] = { 0x55, 0xaa, 0x66, 0x99 };

   to

   const uint8_t expected[] = { 0x55, 0xaa, 0x66, 0x22 };

6. west flash
7. see prints Booting Zephyr OS build zephyr-v3.1.0-3616-g5af932f6e788

ospi-nor-flash@0 SPI flash testing

Test 1: Flash erase Flash erase succeeded!

Test 2: Flash write Attempting to write 4 bytes Data read does not match data written!! 000ff000 wrote 55 read 55 match 000ff001 wrote aa read aa match 000ff002 wrote 66 read 66 match 000ff003 wrote 22 read 00 MISMATCH

Expected behavior Test should every time even if written data is changed.

Impact One bit mode is not fully working.

Logs and console output

Environment (please complete the following information):

• OS: Windows
• Toolchain (e.g Zephyr SDK, ...)
• Commit SHA or Version used

Additional context Add any other context that could be relevant to your issue, such as pin setting, target configuration, ...

[FRASTM]

With f2c49619d2698a1abbeab62e5596a676938c863f, $ west build -p auto -b b_u585i_iot02a samples/drivers/spi_flash gives the following output in the conditions of this issue:

OSPI flash config is SPI|DUAL|QUAD / STR                                       
*** Booting Zephyr OS build zephyr-v3.1.0-3609-gf2c49619d269  ***              

ospi-nor-flash@0 SPI flash testing                                             
==========================                                                     

Test 1: Flash erase                                                            
Flash erase succeeded!                                                         

Test 2: Flash write                                                            
Attempting to write 4 bytes                                                    
 Wr : 55, aa, 66, 22                                                           
Data read matches data written. Good!!                                         
 Rd : 55, aa, 66, 22  

but error occur after changing the data afterwards

[JiiZR]

Did you try all steps from 1 to 7 to reproduce problem ?

[FRASTM]

Yes, the pb comes from the AddressSize when erasing in SPI mode : should be 24 bits but is uncorrectly set to 32bits. Looking in the SDFP table when processing the data to configure the spi_nor_process_bfp_addrbytes

[FRASTM]

could you try with the following patch:

diff --git a/drivers/flash/flash_stm32_ospi.c b/drivers/flash/flash_stm32_ospi.c
index da27823be5..6a2b951fff 100644
--- a/drivers/flash/flash_stm32_ospi.c
+++ b/drivers/flash/flash_stm32_ospi.c
@@ -819,8 +819,11 @@ static int flash_stm32_ospi_erase(const struct device *dev, off_t addr,
                        (dev_cfg->data_rate == OSPI_DTR_TRANSFER)
                        ? HAL_OSPI_ADDRESS_DTR_ENABLE
                        : HAL_OSPI_ADDRESS_DTR_DISABLE;
-                   cmd_erase.AddressSize = stm32_ospi_hal_address_size(dev);
                    cmd_erase.Address = addr;
+                   cmd_erase.AddressSize =
+                       (dev_cfg->data_mode == OSPI_OPI_MODE)
+                       ? stm32_ospi_hal_address_size(dev)
+                       : HAL_OSPI_ADDRESS_24_BITS;
                }
            }

[JiiZR]

Fix corrects the erase problem, thanks.