Open SgrrZhf opened 11 months ago
Awesome! I would like to help with this, I'm currently working on a project using the RP2040, one of the only duel core M's around. If I give the PR a spin with my hardware would be helpful?
If there is any other way I can be of assistance I'm all ears.
Awesome! I would like to help with this, I'm currently working on a project using the RP2040, one of the only duel core M's around. If I give the PR a spin with my hardware would be helpful?
So, I guess you must be interested in this https://github.com/zephyrproject-rtos/zephyr/issues/59826 @o7-machinehum
@SgrrZhf The linked issues in the description here have all been merged. Is there remaining work, or can this issue be closed?
Yes, most of these have been finished. But there is something left, I marked them out in the description.
Is your enhancement proposal related to a problem? Please describe. When I separated the Cortex-M and Cortex-A/R aarch32 architecture code, I found some improvements that can be made. So I list them here for me or other interested people.
Describe the solution you'd like
Additional context
More details for the list above.
SMP support for Cortex-A/R
[x] Refine the exception entry and exit code. https://github.com/zephyrproject-rtos/zephyr/pull/61206 Cortex-A/R arch32 has 5 exceptions. svc, fiq, irq, abt, und. The exception entry and exit code can be unified.
[x] Distinguish interrupt nested count and exception nested count. For now, The Cortex-A/R code doesn't distinguish interrupt nested count and exception nested count. It will cause some issues with the context switch. For example, when IRQ occurred in an SVC handler routing, a context switch could happen after handling IRQ, but now it cannot occur because of nested count >= 1.