dts: arm: st: u5: incorrect lptim2 clock enable bit

Describe the bug

For the STM32U5 The LPTIM2 clock enable should be bit 5 of RCC APB1 clock enable register 2 (RM0456 Rev 4 11.8.34).

See #63655 for fix.

To Reproduce

Enable LPTIM2 using the address currently in the device tree and run an application with PM enabled.

Example overlay:

&lptim2 {
       clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000200>,
                <&rcc STM32_SRC_LSE LPTIM2_SEL(3)>;
       status = "okay";
};

Example config:

CONFIG_SYS_CLOCK_TICKS_PER_SEC=4096

west build -p -b nucleo_u575zi_q zephyr/samples/boards/stm32/power_mgmt/blinky

The application will hang at boot waiting for the clock to be enabled.

Expected behavior

Use the correct register bit and the application runs as expected.

&lptim2 {
       clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000020>,
                <&rcc STM32_SRC_LSE LPTIM2_SEL(3)>;
       status = "okay";
};

Impact

LPTIM2 cannot be used. Trivial fix.

Environment (please complete the following information):

Notes:

There might also be an issue with the use of the st,static-prescaler property on LPTIM2. I will submit another issue or discussion for this.

zephyrproject-rtos / zephyr