soc: power: stm32l4: SRAM3 Retention in STOP2 mode

[coran21]

I'm working on quite a large project, and suddenly, I started getting many different and weird bus errors like "Precise data bus error", "Illegal instruction use" and others. I spent many hours troubleshooting the problems and finally found that it was caused by powering down SRAM3 in the STOP2 mode. One of the main things that helped me is the specific command LL_PWR_DisableSRAM3Retention(); inpower.c file, which caught my attention.

Describe the solution you'd like I would like to set SRAM3 content retention behavior in the configuration or in the device tree.

Describe alternatives you've considered For now, I have to modify power.c file manually to enable SRAM3 content retention.

I can prepare a PR if we agree on how this should be done.

[FRASTM]

@coran21 thanks for raising this behavior. A property in the device Tree is fine to enable/disable the SRAM3 retention capability

[coran21]

@FRASTM I looked into that little bit, and in bindings, I found only memory-controllers and sram. It doesn't seems that it should be in the memory-controllers, and sram has only mmio-sram, which is too generic for this purpose. Could you help me select the right place where to create this new property?

[FRASTM]

Another way could be to set a specific bindings for the stm32l4 for its power-state, not attached to the sram3 compatible = "stm32,stm32l4-power", "zephyr,power-state";

with a property or something like

compatible: "stm32,stm32l4-power"

include: zephyr,power-state.yaml

properties:
  sram-retention:
    type: boolean
    description: |
      SRAM retention during low power mode if true
      SRAM content is lost during low power mode if false