rp2040.dtsi defines wrong number of IRQ priority bits

[renestraub]

Describe the bug

The RP2040 dtsi (zephyr\dts\arm\rpi_pico\rp2040.dtsi) defines the wrong number of IRQ priority bits.

&nvic {
    arm,num-irq-priority-bits = <3>;
};

However RP2040 CM0+ implements only 2 bits. Thus IRQ priority settings are wrong in general. The RPI_PICO_DEFAULT_IRQ_PRIORITY (equals to 3) becomes 1.

From the RP2040 datasheet (build-date: 2023-03-02), section 2.4.5

M0PLUS: NVIC_IPR0 Register
Offset: 0xe400
Description
Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest
priority, and 3 is the lowest.
Note: Writing 1 to an NVIC_ICPR bit does not affect the active state of the corresponding interrupt.
These registers are only word-accessible

Expected behavior

• number of IRQ priority bits = 2
• RPI_PICO_DEFAULT_IRQ_PRIORITY (defined as 3) correctly configured in NVIC_ICP registers.
• NVIC_IPR[0..3] Prio Values = 3, instead of 1

&nvic {
    arm,num-irq-priority-bits = <2>;
};

Impact IRQ priorities don't work as expected. RPI_PICO_DEFAULT_IRQ_PRIORITY (defined as 3) becomes 1.

Logs and console output

**Environment - OS: Windows - Zephyr SDK - * 1a0b1124c6 - (13 days ago) MAINTAINERS: charger: Adds entry for "Chargers" - Ricardo Rivera-Matos (HEAD -> main, origin/main, origin/HEAD)

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[yonsch]

@renestraub Thanks for reporting this! Fixed here: #65785