search

zephyrproject-rtos / zephyr

Primary Git Repository for the Zephyr Project. Zephyr is a new generation, scalable, optimized, secure RTOS for multiple hardware architectures.
https://docs.zephyrproject.org
Apache License 2.0
10.64k stars 6.52k forks source link

ARC SMP mode doesn't initialize MPU to all cores #68341

Open avivbarkan opened 8 months ago

avivbarkan commented 8 months ago

Describe the bug Running ARC HS48x, dual core with SMP and multi-threading enabled. It seems that the function _arc_mpuinit being called for core-0 only. That means that for core-1 the MPU remains disabled the default access attributes are being used.

This caused a problem not only when accessing a forbidden area but also when the attributes of ranges being changed. For example if the NV bit is set.

In my case we change a memory are to be un-cached area. In this the range was set as un-cached for core-0 and cached for core-1

github-actions[bot] commented 8 months ago

Hi @avivbarkan! We appreciate you submitting your first issue for our open-source project. 🌟

Even though I'm a bot, I can assure you that the whole community is genuinely grateful for your time and effort. 🤖💙

ruuddw commented 8 months ago

Acknowledged, so far we didn't support configurations with MPU. What MPU features are most important to you? The cache attributes? I'll see what we can do to add MPU support for SMP, would you be able/willing to prepare a PR for this?

avivbarkan commented 8 months ago

Hi, What we are trying to get is the same MPU configuration for both cores in SMP mode. I'm referring to the configuration that being done as part of the setting defined in the _mpuregions (_arc_mpuregions.c).

I don't really have a PR for it. We just worked around it by adding an additional call to _arc_mpuinit in _z_arc_slavestart function (_arcsmp.c)