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Primary Git Repository for the Zephyr Project. Zephyr is a new generation, scalable, optimized, secure RTOS for multiple hardware architectures.
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Need help to add mb1835b DSI display for board stm32u5a9j_dk and Introduce STM32U5 DSI host driver #71790

Open jn-coueron-muxen opened 6 months ago

jn-coueron-muxen commented 6 months ago

The display of STM32U5A9J-DK Discovery kit is not yet supported on zephyr. Today It's not possible to use the display because the dts and the display driver doesnt exists on zephyr

I wish to be able to use the STM32U5A9J-DK Discovery kit with the sample lvgl for example

The alternative is to use the stm32Cube I have done a small project with stm32cube to check the display working, but i love zephyr to much to use stm32cube for my project.

Additional context I'm trying to add the support of the STM32U5A9J-DK Discovery kit's display. My work is avaible here : https://github.com/jn-coueron-muxen/zephyr/tree/zephyr-ltdc-dsi-stm32u5a9j-dk

No build Error, No execution Error But the screen is still black. The only thing visible is the activation of the backlight :

https://github.com/zephyrproject-rtos/zephyr/assets/163851055/f924ad7d-e86a-4493-ae06-80cfc37e57e0

Ressources used The hx8379 driver code is based on the code of hx8394 and the code from stm32u5x9j-dk-bsp from @STMicroelectronics

The display controller is a hx8379 from Himax. (proof here) The datasheet of the hx8379 to name and comment the cmd sended to the screen. The reference manual of the stm32u5 (rm0456) The work done in zephyr for the stm32h7.

Need help I don't known if the problem is on the host part or if it's my display driver is not working. What test can i done to validate one part or an other ? I need help and advices, maybe from @dariis and @FRASTM who's worked on the stm32h747i_disco or anyone (@ABOSTM, @erwango, @danieldegrasse, @marcusfolkesson) want to help my adding this display on zephyr.

My Log Trace

[00:00:00.134,000] <dbg> dsi_stm32: mipi_dsi_stm32_log_config: DISPLAY: pix 20833 kHz, lane 62500 kHz
[00:00:00.134,000] <dbg> dsi_stm32: mipi_dsi_stm32_log_config: HAL_DSI_Init setup:
[00:00:00.134,000] <dbg> dsi_stm32: mipi_dsi_stm32_log_config:   AutomaticClockLaneControl 0x0
[00:00:00.134,000] <dbg> dsi_stm32: mipi_dsi_stm32_log_config:   TXEscapeCkdiv 4
[00:00:00.134,000] <dbg> dsi_stm32: mipi_dsi_stm32_log_config:   NumberOfLanes 1
[00:00:00.134,000] <dbg> dsi_stm32: mipi_dsi_stm32_log_config:   PLLNDIV 125
[00:00:00.134,000] <dbg> dsi_stm32: mipi_dsi_stm32_log_config:   PLLIDF 4
[00:00:00.134,000] <dbg> dsi_stm32: mipi_dsi_stm32_log_config:   PLLODF 2
[00:00:00.134,000] <dbg> dsi_stm32: mipi_dsi_stm32_log_config: HAL_DSI_ConfigVideoMode setup:
[00:00:00.134,000] <dbg> dsi_stm32: mipi_dsi_stm32_log_config:   VirtualChannelID 0
[00:00:00.134,000] <dbg> dsi_stm32: mipi_dsi_stm32_log_config:   ColorCoding 0x5
[00:00:00.134,000] <dbg> dsi_stm32: mipi_dsi_stm32_log_config:   LooselyPacked 0x0
[00:00:00.134,000] <dbg> dsi_stm32: mipi_dsi_stm32_log_config:   Mode 0x2
[00:00:00.134,000] <dbg> dsi_stm32: mipi_dsi_stm32_log_config:   PacketSize 480
[00:00:00.134,000] <dbg> dsi_stm32: mipi_dsi_stm32_log_config:   NumberOfChunks 0
[00:00:00.134,000] <dbg> dsi_stm32: mipi_dsi_stm32_log_config:   NullPacketSize 4095
[00:00:00.134,000] <dbg> dsi_stm32: mipi_dsi_stm32_log_config:   HSPolarity 0x0
[00:00:00.134,000] <dbg> dsi_stm32: mipi_dsi_stm32_log_config:   VSPolarity 0x0
[00:00:00.134,000] <dbg> dsi_stm32: mipi_dsi_stm32_log_config:   DEPolarity 0x0
[00:00:00.134,000] <dbg> dsi_stm32: mipi_dsi_stm32_log_config:   HorizontalSyncActive 6
[00:00:00.134,000] <dbg> dsi_stm32: mipi_dsi_stm32_log_config:   HorizontalBackPorch 3
[00:00:00.134,000] <dbg> dsi_stm32: mipi_dsi_stm32_log_config:   HorizontalLine 1452
[00:00:00.134,000] <dbg> dsi_stm32: mipi_dsi_stm32_log_config:   VerticalSyncActive 1
[00:00:00.134,000] <dbg> dsi_stm32: mipi_dsi_stm32_log_config:   VerticalBackPorch 12
[00:00:00.134,000] <dbg> dsi_stm32: mipi_dsi_stm32_log_config:   VerticalFrontPorch 50
[00:00:00.134,000] <dbg> dsi_stm32: mipi_dsi_stm32_log_config:   VerticalActive 481
[00:00:00.134,000] <dbg> dsi_stm32: mipi_dsi_stm32_log_config:   LPCommandEnable 0x8000
[00:00:00.134,000] <dbg> dsi_stm32: mipi_dsi_stm32_log_config:   LPLargestPacketSize 64
[00:00:00.134,000] <dbg> dsi_stm32: mipi_dsi_stm32_log_config:   LPVACTLargestPacketSize 0
[00:00:00.135,000] <dbg> dsi_stm32: mipi_dsi_stm32_log_config:   LPHorizontalFrontPorchEnable 0x2000
[00:00:00.135,000] <dbg> dsi_stm32: mipi_dsi_stm32_log_config:   LPHorizontalBackPorchEnable 0x1000
[00:00:00.135,000] <dbg> dsi_stm32: mipi_dsi_stm32_log_config:   LPVerticalActiveEnable 0x800
[00:00:00.135,000] <dbg> dsi_stm32: mipi_dsi_stm32_log_config:   LPVerticalFrontPorchEnable 0x400
[00:00:00.135,000] <dbg> dsi_stm32: mipi_dsi_stm32_log_config:   LPVerticalBackPorchEnable 0x200
[00:00:00.135,000] <dbg> dsi_stm32: mipi_dsi_stm32_log_config:   LPVerticalSyncActiveEnable 0x100
[00:00:00.135,000] <dbg> dsi_stm32: mipi_dsi_stm32_log_config:   FrameBTAAcknowledgeEnable 0x4000
[00:00:00.135,000] <dbg> dsi_stm32: mipi_dsi_stm32_log_config: HAL_DSI_ConfigHostTimeouts:
[00:00:00.135,000] <dbg> dsi_stm32: mipi_dsi_stm32_log_config:   TimeoutCkdiv 1
[00:00:00.135,000] <dbg> dsi_stm32: mipi_dsi_stm32_log_config:   HighSpeedTransmissionTimeout 0
[00:00:00.135,000] <dbg> dsi_stm32: mipi_dsi_stm32_log_config:   LowPowerReceptionTimeout 0
[00:00:00.135,000] <dbg> dsi_stm32: mipi_dsi_stm32_log_config:   HighSpeedReadTimeout 0
[00:00:00.135,000] <dbg> dsi_stm32: mipi_dsi_stm32_log_config:   LowPowerReadTimeout 0
[00:00:00.135,000] <dbg> dsi_stm32: mipi_dsi_stm32_log_config:   HighSpeedWriteTimeout 0
[00:00:00.135,000] <dbg> dsi_stm32: mipi_dsi_stm32_log_config:   HighSpeedWritePrespMode 0
[00:00:00.135,000] <dbg> dsi_stm32: mipi_dsi_stm32_log_config:   LowPowerWriteTimeout 0
[00:00:00.135,000] <dbg> dsi_stm32: mipi_dsi_stm32_log_config:   BTATimeout 0
[00:00:00.135,000] <dbg> dsi_stm32: mipi_dsi_stm32_log_config: HAL_DSI_ConfigPhyTimer:
[00:00:00.135,000] <dbg> dsi_stm32: mipi_dsi_stm32_log_config:   ClockLaneHS2LPTime 11
[00:00:00.135,000] <dbg> dsi_stm32: mipi_dsi_stm32_log_config:   ClockLaneLP2HSTime 40
[00:00:00.135,000] <dbg> dsi_stm32: mipi_dsi_stm32_log_config:   DataLaneHS2LPTime 12
[00:00:00.135,000] <dbg> dsi_stm32: mipi_dsi_stm32_log_config:   DataLaneLP2HSTime 23
[00:00:00.135,000] <dbg> dsi_stm32: mipi_dsi_stm32_log_config:   DataLaneMaxReadTime 0
[00:00:00.135,000] <dbg> dsi_stm32: mipi_dsi_stm32_log_config:   StopWaitTime 7
[00:00:00.135,000] <dbg> dsi_stm32: mipi_dsi_stm32_transfer: TX: ch   0, reg 0x00, len  4
                                    b9 ff 83 79                                      |...y             
[00:00:00.135,000] <dbg> dsi_stm32: mipi_dsi_stm32_transfer: TX: ch   0, reg 0x00, len 17
                                    b1 44 1c 1c 37 57 90 d0  e2 58 80 38 38 80 33 34 |.D..7W.. .X.88.34
                                    42                                               |B                
[00:00:00.135,000] <dbg> dsi_stm32: mipi_dsi_stm32_transfer: TX: ch   0, reg 0x00, len 10
                                    b2 80 14 0c 30 20 50 11  42 1d                   |....0 P. B.      
[00:00:00.140,000] <dbg> dsi_stm32: mipi_dsi_stm32_transfer: TX: ch   0, reg 0x00, len 11
                                    b4 01 aa 01 af 01 af 10  ea 1c ea                |........ ...     
[00:00:00.140,000] <dbg> dsi_stm32: mipi_dsi_stm32_transfer: TX: ch   0, reg 0x00, len  5
                                    c7 00 00 00 c0                                   |.....            
[00:00:00.140,000] <dbg> dsi_stm32: mipi_dsi_stm32_transfer: TX: ch   0, reg 0x00, len  2
                                    cc 02                                            |..               
[00:00:00.140,000] <dbg> dsi_stm32: mipi_dsi_stm32_transfer: TX: ch   0, reg 0x00, len  2
                                    d2 77                                            |.w               
[00:00:00.140,000] <dbg> dsi_stm32: mipi_dsi_stm32_transfer: TX: ch   0, reg 0x00, len 38
                                    d3 00 07 00 00 00 08 08  32 10 01 00 01 03 72 03 |........ 2.....r.
                                    72 00 08 00 08 33 33 05  05 37 05 05 37 0a 00 00 |r....33. .7..7...
                                    00 0a 00 01 00 0e                                |......           
[00:00:00.140,000] <dbg> dsi_stm32: mipi_dsi_stm32_transfer: TX: ch   0, reg 0x00, len 35
                                    d5 18 18 18 18 18 18 18  18 19 19 18 18 18 18 19 |........ ........
                                    19 01 00 03 02 05 04 07  06 23 22 21 20 18 18 18 |........ .#"! ...
                                    18 00 00                                         |...              
[00:00:00.140,000] <dbg> dsi_stm32: mipi_dsi_stm32_transfer: TX: ch   0, reg 0x00, len 33
                                    d6 18 18 18 18 18 18 18  18 19 19 18 18 19 19 18 |........ ........
                                    18 06 07 04 05 02 03 00  01 20 21 22 23 18 18 18 |........ . !"#...
                                    18                                               |.                
[00:00:00.140,000] <dbg> dsi_stm32: mipi_dsi_stm32_transfer: TX: ch   0, reg 0x00, len 43
                                    e0 00 16 1b 30 36 3f 24  40 09 0d 0f 18 0e 11 12 |....06?$ @.......
                                    11 14 07 12 13 18 00 17  1c 30 36 3f 24 40 09 0c |........ .06?$@..
                                    0f 18 0e 11 14 11 12 07  12 14 18                |........ ...     
[00:00:00.141,000] <dbg> dsi_stm32: mipi_dsi_stm32_transfer: TX: ch   0, reg 0x00, len  4
                                    b6 2c 92 00                                      |.,..             
[00:00:00.141,000] <dbg> dsi_stm32: mipi_dsi_stm32_transfer: TX: ch   0, reg 0x00, len  2
                                    bd 02                                            |..               
[00:00:00.151,000] <dbg> dsi_stm32: mipi_dsi_stm32_transfer: TX: ch   0, reg 0x00, len 43
                                    c1 00 09 0f 18 21 2a 34  3c 45 4c 56 5e 66 6e 76 |.....!*4 <ELV^fnv
                                    7e 87 8e 95 9d a6 af b7  bd c5 ce d5 df e7 ee f4 |~....... ........
                                    fa ff 0c 31 83 3c 5b 56  1e 5a ff                |...1.<[V .Z.     
[00:00:00.151,000] <dbg> dsi_stm32: mipi_dsi_stm32_transfer: TX: ch   0, reg 0x00, len  2
                                    bd 00                                            |..               
[00:00:00.151,000] <dbg> dsi_stm32: mipi_dsi_stm32_transfer: TX: ch   0, reg 0x00, len  2
                                    bd 01                                            |..               
[00:00:00.151,000] <dbg> dsi_stm32: mipi_dsi_stm32_transfer: TX: ch   0, reg 0x00, len 43
                                    c1 00 08 0f 16 1f 28 31  39 41 48 51 59 60 68 70 |......(1 9AHQY`hp
                                    78 7f 87 8d 94 9c a3 ab  b3 b9 c1 c8 d0 d8 e0 e8 |x....... ........
                                    ee f5 3b 1a b6 a0 07 45  c5 37 00                |..;....E .7.     
[00:00:00.151,000] <dbg> dsi_stm32: mipi_dsi_stm32_transfer: TX: ch   0, reg 0x00, len  2
                                    bd 00                                            |..               
[00:00:00.151,000] <dbg> dsi_stm32: mipi_dsi_stm32_transfer: TX: ch   0, reg 0x00, len 44
                                    c1 01 00 07 0f 16 1f 27  30 38 40 47 4e 56 5d 65 |.......' 08@GNV]e
                                    6d 74 7d 84 8a 90 99 a1  a9 b0 b6 bd c4 cd d4 dd |mt}..... ........
                                    e5 ec f3 36 07 1c c0 1b  01 f1 34 00             |...6.... ..4.    
[00:00:00.151,000] <dbg> dsi_stm32: mipi_dsi_stm32_transfer: TX: ch   0, reg 0x11, len  0
[00:00:00.271,000] <dbg> dsi_stm32: mipi_dsi_stm32_transfer: TX: ch   0, reg 0x29, len  0
*** Booting Zephyr OS build 1a35bc844862 ***
github-actions[bot] commented 6 months ago

Hi @jn-coueron-muxen! We appreciate you submitting your first issue for our open-source project. 🌟

Even though I'm a bot, I can assure you that the whole community is genuinely grateful for your time and effort. 🤖💙

ajarmouni-st commented 6 months ago

Hi @jn-coueron-muxen, there is this small quirk in case you are not aware of it

"The microcontroller software system must invert DSI.CK_N and DSI.CK_P lines together to align with DSI_V3 add-on boards. The DSI clock differential signals (_N and _P) are inverted on CN2 for layout reasons."

section 8.1 https://www.st.com/resource/en/user_manual/um2967-discovery-kits-with-stm32u5x9nj-mcus-stmicroelectronics.pdf