Closed danieldegrasse closed 3 days ago
@matt-wood-ct, I have tested this PR by checking the frequency of a pin toggled every 25ms (using k_msleep
for the delay) on an oscilloscope. I see a period of 50.20ms, which I believe should be close enough to the target period that the additional delays are likely due to code overhead. Can you verify this change on your hardware?
@matt-wood-ct, I have tested this PR by checking the frequency of a pin toggled every 25ms (using
k_msleep
for the delay) on an oscilloscope. I see a period of 50.20ms, which I believe should be close enough to the target period that the additional delays are likely due to code overhead. Can you verify this change on your hardware?
Great work, I will give this a go when I'm back in the office tomorrow, thanks for your work on this your solution looks pretty elegant.
@matt-wood-ct, I have tested this PR by checking the frequency of a pin toggled every 25ms (using
k_msleep
for the delay) on an oscilloscope. I see a period of 50.20ms, which I believe should be close enough to the target period that the additional delays are likely due to code overhead. Can you verify this change on your hardware?
Hi Daniel, I switched over to your fix branch and adjusted my project to suit (I'm still pre HW model 2) but unfortunately I'm getting significant time drift. Test method:
After 4 minutes it was 25 seconds out, imx reported 3m35s.
But perhaps more concerningly I get these errors out on boot:
[00:00:00.001,000] <err> mcux_gpt: Cannot Adjust GPT freq to 25000000
[00:00:00.001,000] <err> mcux_gpt: clock src is 66000000
My out of tree board file does not configure systick or the gpt at all beyond the obligatory:
&gpt_hw_timer {
status = "okay";
};
&systick {
status = "okay";
};
My out of tree board file does not configure systick or the gpt at all beyond the obligatory
Just a note here- the gpt_hw_timer
node isn't the one you want enabled in order to use the GPT as a counter driver- the GPT can either be a system timer source (only useful for low power modes) or just a hardware counter. Are you changing the compatible (and clocks) property on that node to use it with the GPT counter driver?
But perhaps more concerningly I get these errors out on boot:
This looks like the peripheral clock is being reported at 66MHz, which is expected here given that the core clock has dropped from 600MHz to 528MHz. I'd recommend setting the gptfreq
property of the GPT node to 33MHz (instead of the default 25MHz), as the GPT will be able to find a divider for this frequency given the new peripheral clock. I've pushed an update to this PR to make that change on the RT1040 for the GPT2 counter.
After 4 minutes it was 25 seconds out, imx reported 3m35s.
This is more concerning. What values are set in your application for the following registers?
CCM->CBCMR
(expect 0xf5a29104
)CCM->CBCDR
(expect 0x18340
)Based on the log you sent, it does seem like the PERCLK_CLK_ROOT is being set correctly (so the AHB_CLK_ROOT probably is too). Maybe check the value of CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC
?
In particular, make sure that CBCMR[PRE_PERIPH_CLK_SEL]
is set to 0b00
. this will differ from other iMX RT parts, where the PLL1 (ARM PLL) is used for the clock source, and CBCMR[PRE_PERIPH_CLK_SEL]
is set to 0b11
.
I tried a similar test to yours with a stopwatch over one minute, and checked uptime at 30 seconds and 60 seconds:
uart:~$ kernel uptime
Uptime: 30334 ms
uart:~$ kernel uptime
Uptime: 60356 ms
uart:~$
Apologies for the delay, thanks for the additional fixes, I have rerun the test using your new version.
I can confirm your adjustment of the GPT did resolve my boot errors and the timers appear to be functioning well (if my boards piezo tone is anything to go by 😄)
~However I am still experiencing clock drift, around 7 seconds per minute slow still.~
After deleting my cmake output and reloading, rebuilding and retesting this it turns out CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC
was stuck as 600MHz, after the full clean and reload it is now 528MHz and uptime reports correctly.
I've attached the debugger and captured the registers you mentioned, values below.
CCM->CBCMR = 0xFDA29114 CCM->CBCDR = 0x00018340
Full CCM register dump:
Peripheral, Register, Value, Fields
CCM, CCR, 0x0401107F, OSCNT: 0b01111111; COSC_EN: COSC_EN_1; REG_BYPASS_COUNT: 0b100000; RBC_EN: RBC_EN_0
CCM, CSR, 0x00000038, REF_EN_B: REF_EN_B_0; CAMP2_READY: CAMP2_READY_1; COSC_READY: COSC_READY_1
CCM, CCSR, 0x00000100, PLL3_SW_CLK_SEL: PLL3_SW_CLK_SEL_0
CCM, CACRR, 0x00000000, ARM_PODF: ARM_PODF_0
CCM, CBCDR, 0x00018340, SEMC_CLK_SEL: SEMC_CLK_SEL_1; SEMC_ALT_CLK_SEL: SEMC_ALT_CLK_SEL_0; IPG_PODF: IPG_PODF_3; AHB_PODF: AHB_PODF_0; SEMC_PODF: SEMC_PODF_1; PERIPH_CLK_SEL: PERIPH_CLK_SEL_0; PERIPH_CLK2_PODF: PERIPH_CLK2_PODF_0
CCM, CBCMR, 0xFDA29114, LPSPI_CLK_SEL: LPSPI_CLK_SEL_1; FLEXSPI2_CLK_SEL: FLEXSPI2_CLK_SEL_1; PERIPH_CLK2_SEL: PERIPH_CLK2_SEL_1; TRACE_CLK_SEL: TRACE_CLK_SEL_2; PRE_PERIPH_CLK_SEL: PRE_PERIPH_CLK_SEL_0; LCDIF_PODF: LCDIF_PODF_3; LPSPI_PODF: LPSPI_PODF_7; FLEXSPI2_PODF: FLEXSPI2_PODF_7
CCM, CSCMR1, 0x66930001, PERCLK_PODF: DIVIDE_2; PERCLK_CLK_SEL: PERCLK_CLK_SEL_0; SAI1_CLK_SEL: SAI1_CLK_SEL_0; SAI2_CLK_SEL: SAI2_CLK_SEL_0; SAI3_CLK_SEL: SAI3_CLK_SEL_0; USDHC1_CLK_SEL: USDHC1_CLK_SEL_1; USDHC2_CLK_SEL: USDHC2_CLK_SEL_1; FLEXSPI_PODF: FLEXSPI_PODF_5; FLEXSPI_CLK_SEL: FLEXSPI_CLK_SEL_3
CCM, CSCMR2, 0x13192F06, CAN_CLK_PODF: DIVIDE_2; CAN_CLK_SEL: CAN_CLK_SEL_3; FLEXIO2_CLK_SEL: FLEXIO2_CLK_SEL_3
CCM, CSCDR1, 0x06490B00, UART_CLK_PODF: DIVIDE_1; UART_CLK_SEL: UART_CLK_SEL_0; USDHC1_PODF: USDHC1_PODF_1; USDHC2_PODF: USDHC2_PODF_1; TRACE_PODF: TRACE_PODF_3
CCM, CS1CDR, 0x0EC102C1, SAI1_CLK_PODF: DIVIDE_2; SAI1_CLK_PRED: SAI1_CLK_PRED_3; FLEXIO2_CLK_PRED: FLEXIO2_CLK_PRED_1; SAI3_CLK_PODF: DIVIDE_2; SAI3_CLK_PRED: SAI3_CLK_PRED_3; FLEXIO2_CLK_PODF: DIVIDE_8
CCM, CS2CDR, 0x000736C1, SAI2_CLK_PODF: DIVIDE_2; SAI2_CLK_PRED: SAI2_CLK_PRED_3
CCM, CDCDR, 0x33F71F92, FLEXIO1_CLK_SEL: FLEXIO1_CLK_SEL_3; FLEXIO1_CLK_PODF: DIVIDE_8; FLEXIO1_CLK_PRED: DIVIDE_2; SPDIF0_CLK_SEL: SPDIF0_CLK_SEL_3; SPDIF0_CLK_PODF: DIVIDE_8; SPDIF0_CLK_PRED: DIVIDE_2
CCM, CSCDR2, 0x00029150, LCDIF_PRED: LCDIF_PRED_1; LCDIF_PRE_CLK_SEL: LCDIF_PRE_CLK_SEL_5; LPI2C_CLK_SEL: LPI2C_CLK_SEL_0; LPI2C_CLK_PODF: DIVIDE_1
CCM, CSCDR3, 0x00030841
CCM, CDHIPR, 0x00000000, SEMC_PODF_BUSY: SEMC_PODF_BUSY_0; AHB_PODF_BUSY: AHB_PODF_BUSY_0; PERIPH2_CLK_SEL_BUSY: PERIPH2_CLK_SEL_BUSY_0; PERIPH_CLK_SEL_BUSY: PERIPH_CLK_SEL_BUSY_0; ARM_PODF_BUSY: ARM_PODF_BUSY_0
CCM, CLPCR, 0x00000078, LPM: LPM_0; ARM_CLK_DIS_ON_LPM: ARM_CLK_DIS_ON_LPM_1; SBYOS: SBYOS_1; DIS_REF_OSC: DIS_REF_OSC_0; VSTBY: VSTBY_0; STBY_COUNT: STBY_COUNT_0; COSC_PWRDOWN: COSC_PWRDOWN_0; BYPASS_LPM_HS1: 0b0; BYPASS_LPM_HS0: 0b0; MASK_CORE0_WFI: MASK_CORE0_WFI_0; MASK_SCU_IDLE: MASK_SCU_IDLE_0; MASK_L2CC_IDLE: MASK_L2CC_IDLE_0
CCM, CISR, 0x04D20000, LRF_PLL: LRF_PLL_0; COSC_READY: COSC_READY_0; SEMC_PODF_LOADED: SEMC_PODF_LOADED_1; PERIPH2_CLK_SEL_LOADED: PERIPH2_CLK_SEL_LOADED_0; AHB_PODF_LOADED: AHB_PODF_LOADED_1; PERIPH_CLK_SEL_LOADED: PERIPH_CLK_SEL_LOADED_1; ARM_PODF_LOADED: ARM_PODF_LOADED_1
CCM, CIMR, 0xFFFFFFFF, MASK_LRF_PLL: MASK_LRF_PLL_1; MASK_COSC_READY: MASK_COSC_READY_1; MASK_SEMC_PODF_LOADED: MASK_SEMC_PODF_LOADED_1; MASK_PERIPH2_CLK_SEL_LOADED: MASK_PERIPH2_CLK_SEL_LOADED_1; MASK_AHB_PODF_LOADED: MASK_AHB_PODF_LOADED_1; MASK_PERIPH_CLK_SEL_LOADED: MASK_PERIPH_CLK_SEL_LOADED_1; ARM_PODF_LOADED: ARM_PODF_LOADED_1
CCM, CCOSR, 0x000A0001, CLKO1_SEL: CLKO1_SEL_1; CLKO1_DIV: CLKO1_DIV_0; CLKO1_EN: CLKO1_EN_0; CLK_OUT_SEL: CLK_OUT_SEL_0; CLKO2_SEL: 0b01010; CLKO2_DIV: CLKO2_DIV_0; CLKO2_EN: CLKO2_EN_0
CCM, CGPR, 0x0000FE62, PMIC_DELAY_SCALER: PMIC_DELAY_SCALER_0; EFUSE_PROG_SUPPLY_GATE: EFUSE_PROG_SUPPLY_GATE_0; SYS_MEM_DS_CTRL: SYS_MEM_DS_CTRL_2; FPL: FPL_0; INT_MEM_CLK_LPM: INT_MEM_CLK_LPM_0
CCM, CCGR0, 0xFFFFFFFF, CG0: 0b11; CG1: 0b11; CG2: 0b11; CG3: 0b11; CG4: 0b11; CG5: 0b11; CG6: 0b11; CG7: 0b11; CG8: 0b11; CG9: 0b11; CG10: 0b11; CG11: 0b11; CG12: 0b11; CG13: 0b11; CG14: 0b11; CG15: 0b11
CCM, CCGR1, 0xFFFFCFFF, CG0: 0b11; CG1: 0b11; CG2: 0b11; CG3: 0b11; CG4: 0b11; CG5: 0b11; CG6: 0b00; CG7: 0b11; CG8: 0b11; CG9: 0b11; CG10: 0b11; CG11: 0b11; CG12: 0b11; CG13: 0b11; CG14: 0b11; CG15: 0b11
CCM, CCGR2, 0xFFFFFFFF, CG0: 0b11; CG1: 0b11; CG2: 0b11; CG3: 0b11; CG4: 0b11; CG5: 0b11; CG6: 0b11; CG7: 0b11; CG8: 0b11; CG9: 0b11; CG10: 0b11; CG11: 0b11; CG12: 0b11; CG13: 0b11; CG14: 0b11; CG15: 0b11
CCM, CCGR3, 0xFFFFFFFF, CG0: 0b11; CG1: 0b11; CG2: 0b11; CG3: 0b11; CG4: 0b11; CG5: 0b11; CG6: 0b11; CG7: 0b11; CG8: 0b11; CG9: 0b11; CG10: 0b11; CG11: 0b11; CG12: 0b11; CG13: 0b11; CG14: 0b11; CG15: 0b11
CCM, CCGR4, 0xFFFFFFFF, CG0: 0b11; CG1: 0b11; CG2: 0b11; CG3: 0b11; CG4: 0b11; CG5: 0b11; CG6: 0b11; CG7: 0b11; CG8: 0b11; CG9: 0b11; CG10: 0b11; CG11: 0b11; CG12: 0b11; CG13: 0b11; CG14: 0b11; CG15: 0b11
CCM, CCGR5, 0xFFFFFFFF, CG0: 0b11; CG1: 0b11; CG2: 0b11; CG3: 0b11; CG4: 0b11; CG5: 0b11; CG6: 0b11; CG7: 0b11; CG8: 0b11; CG9: 0b11; CG10: 0b11; CG11: 0b11; CG12: 0b11; CG13: 0b11; CG14: 0b11; CG15: 0b11
CCM, CCGR6, 0xFFFFFFFF, CG0: 0b11; CG1: 0b11; CG2: 0b11; CG3: 0b11; CG4: 0b11; CG5: 0b11; CG6: 0b11; CG7: 0b11; CG8: 0b11; CG9: 0b11; CG10: 0b11; CG11: 0b11; CG12: 0b11; CG13: 0b11; CG14: 0b11; CG15: 0b11
CCM, CCGR7, 0xFFFFFFFF, CG0: 0b11; CG1: 0b11; CG2: 0b11; CG3: 0b11; CG4: 0b11; CG5: 0b11; CG6: 0b11
CCM, CMEOR, 0x7FFFFFFF, MOD_EN_OV_GPT: MOD_EN_OV_GPT_1; MOD_EN_OV_PIT: MOD_EN_OV_PIT_1; MOD_EN_USDHC: MOD_EN_USDHC_1; MOD_EN_OV_TRNG: MOD_EN_OV_TRNG_1; MOD_EN_OV_CANFD_CPI: MOD_EN_OV_CANFD_CPI_1; MOD_EN_OV_CAN2_CPI: MOD_EN_OV_CAN2_CPI_1; MOD_EN_OV_CAN1_CPI: MOD_EN_OV_CAN1_CPI_1
Apologies for the delay, thanks for the additional fixes, I have rerun the test using your new version. I can confirm your adjustment of the GPT did resolve my boot errors and the timers appear to be functioning well (if my boards piezo tone is anything to go by 😄) ~However I am still experiencing clock drift, around 7 seconds per minute slow still.~ After deleting my cmake output and reloading, rebuilding and retesting this it turns out
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC
was stuck as 600MHz, after the full clean and reload it is now 528MHz and uptime reports correctly.I've attached the debugger and captured the registers you mentioned, values below.
CCM->CBCMR = 0xFDA29114 CCM->CBCDR = 0x00018340
Full CCM register dump:
Peripheral, Register, Value, Fields CCM, CCR, 0x0401107F, OSCNT: 0b01111111; COSC_EN: COSC_EN_1; REG_BYPASS_COUNT: 0b100000; RBC_EN: RBC_EN_0 CCM, CSR, 0x00000038, REF_EN_B: REF_EN_B_0; CAMP2_READY: CAMP2_READY_1; COSC_READY: COSC_READY_1 CCM, CCSR, 0x00000100, PLL3_SW_CLK_SEL: PLL3_SW_CLK_SEL_0 CCM, CACRR, 0x00000000, ARM_PODF: ARM_PODF_0 CCM, CBCDR, 0x00018340, SEMC_CLK_SEL: SEMC_CLK_SEL_1; SEMC_ALT_CLK_SEL: SEMC_ALT_CLK_SEL_0; IPG_PODF: IPG_PODF_3; AHB_PODF: AHB_PODF_0; SEMC_PODF: SEMC_PODF_1; PERIPH_CLK_SEL: PERIPH_CLK_SEL_0; PERIPH_CLK2_PODF: PERIPH_CLK2_PODF_0 CCM, CBCMR, 0xFDA29114, LPSPI_CLK_SEL: LPSPI_CLK_SEL_1; FLEXSPI2_CLK_SEL: FLEXSPI2_CLK_SEL_1; PERIPH_CLK2_SEL: PERIPH_CLK2_SEL_1; TRACE_CLK_SEL: TRACE_CLK_SEL_2; PRE_PERIPH_CLK_SEL: PRE_PERIPH_CLK_SEL_0; LCDIF_PODF: LCDIF_PODF_3; LPSPI_PODF: LPSPI_PODF_7; FLEXSPI2_PODF: FLEXSPI2_PODF_7 CCM, CSCMR1, 0x66930001, PERCLK_PODF: DIVIDE_2; PERCLK_CLK_SEL: PERCLK_CLK_SEL_0; SAI1_CLK_SEL: SAI1_CLK_SEL_0; SAI2_CLK_SEL: SAI2_CLK_SEL_0; SAI3_CLK_SEL: SAI3_CLK_SEL_0; USDHC1_CLK_SEL: USDHC1_CLK_SEL_1; USDHC2_CLK_SEL: USDHC2_CLK_SEL_1; FLEXSPI_PODF: FLEXSPI_PODF_5; FLEXSPI_CLK_SEL: FLEXSPI_CLK_SEL_3 CCM, CSCMR2, 0x13192F06, CAN_CLK_PODF: DIVIDE_2; CAN_CLK_SEL: CAN_CLK_SEL_3; FLEXIO2_CLK_SEL: FLEXIO2_CLK_SEL_3 CCM, CSCDR1, 0x06490B00, UART_CLK_PODF: DIVIDE_1; UART_CLK_SEL: UART_CLK_SEL_0; USDHC1_PODF: USDHC1_PODF_1; USDHC2_PODF: USDHC2_PODF_1; TRACE_PODF: TRACE_PODF_3 CCM, CS1CDR, 0x0EC102C1, SAI1_CLK_PODF: DIVIDE_2; SAI1_CLK_PRED: SAI1_CLK_PRED_3; FLEXIO2_CLK_PRED: FLEXIO2_CLK_PRED_1; SAI3_CLK_PODF: DIVIDE_2; SAI3_CLK_PRED: SAI3_CLK_PRED_3; FLEXIO2_CLK_PODF: DIVIDE_8 CCM, CS2CDR, 0x000736C1, SAI2_CLK_PODF: DIVIDE_2; SAI2_CLK_PRED: SAI2_CLK_PRED_3 CCM, CDCDR, 0x33F71F92, FLEXIO1_CLK_SEL: FLEXIO1_CLK_SEL_3; FLEXIO1_CLK_PODF: DIVIDE_8; FLEXIO1_CLK_PRED: DIVIDE_2; SPDIF0_CLK_SEL: SPDIF0_CLK_SEL_3; SPDIF0_CLK_PODF: DIVIDE_8; SPDIF0_CLK_PRED: DIVIDE_2 CCM, CSCDR2, 0x00029150, LCDIF_PRED: LCDIF_PRED_1; LCDIF_PRE_CLK_SEL: LCDIF_PRE_CLK_SEL_5; LPI2C_CLK_SEL: LPI2C_CLK_SEL_0; LPI2C_CLK_PODF: DIVIDE_1 CCM, CSCDR3, 0x00030841 CCM, CDHIPR, 0x00000000, SEMC_PODF_BUSY: SEMC_PODF_BUSY_0; AHB_PODF_BUSY: AHB_PODF_BUSY_0; PERIPH2_CLK_SEL_BUSY: PERIPH2_CLK_SEL_BUSY_0; PERIPH_CLK_SEL_BUSY: PERIPH_CLK_SEL_BUSY_0; ARM_PODF_BUSY: ARM_PODF_BUSY_0 CCM, CLPCR, 0x00000078, LPM: LPM_0; ARM_CLK_DIS_ON_LPM: ARM_CLK_DIS_ON_LPM_1; SBYOS: SBYOS_1; DIS_REF_OSC: DIS_REF_OSC_0; VSTBY: VSTBY_0; STBY_COUNT: STBY_COUNT_0; COSC_PWRDOWN: COSC_PWRDOWN_0; BYPASS_LPM_HS1: 0b0; BYPASS_LPM_HS0: 0b0; MASK_CORE0_WFI: MASK_CORE0_WFI_0; MASK_SCU_IDLE: MASK_SCU_IDLE_0; MASK_L2CC_IDLE: MASK_L2CC_IDLE_0 CCM, CISR, 0x04D20000, LRF_PLL: LRF_PLL_0; COSC_READY: COSC_READY_0; SEMC_PODF_LOADED: SEMC_PODF_LOADED_1; PERIPH2_CLK_SEL_LOADED: PERIPH2_CLK_SEL_LOADED_0; AHB_PODF_LOADED: AHB_PODF_LOADED_1; PERIPH_CLK_SEL_LOADED: PERIPH_CLK_SEL_LOADED_1; ARM_PODF_LOADED: ARM_PODF_LOADED_1 CCM, CIMR, 0xFFFFFFFF, MASK_LRF_PLL: MASK_LRF_PLL_1; MASK_COSC_READY: MASK_COSC_READY_1; MASK_SEMC_PODF_LOADED: MASK_SEMC_PODF_LOADED_1; MASK_PERIPH2_CLK_SEL_LOADED: MASK_PERIPH2_CLK_SEL_LOADED_1; MASK_AHB_PODF_LOADED: MASK_AHB_PODF_LOADED_1; MASK_PERIPH_CLK_SEL_LOADED: MASK_PERIPH_CLK_SEL_LOADED_1; ARM_PODF_LOADED: ARM_PODF_LOADED_1 CCM, CCOSR, 0x000A0001, CLKO1_SEL: CLKO1_SEL_1; CLKO1_DIV: CLKO1_DIV_0; CLKO1_EN: CLKO1_EN_0; CLK_OUT_SEL: CLK_OUT_SEL_0; CLKO2_SEL: 0b01010; CLKO2_DIV: CLKO2_DIV_0; CLKO2_EN: CLKO2_EN_0 CCM, CGPR, 0x0000FE62, PMIC_DELAY_SCALER: PMIC_DELAY_SCALER_0; EFUSE_PROG_SUPPLY_GATE: EFUSE_PROG_SUPPLY_GATE_0; SYS_MEM_DS_CTRL: SYS_MEM_DS_CTRL_2; FPL: FPL_0; INT_MEM_CLK_LPM: INT_MEM_CLK_LPM_0 CCM, CCGR0, 0xFFFFFFFF, CG0: 0b11; CG1: 0b11; CG2: 0b11; CG3: 0b11; CG4: 0b11; CG5: 0b11; CG6: 0b11; CG7: 0b11; CG8: 0b11; CG9: 0b11; CG10: 0b11; CG11: 0b11; CG12: 0b11; CG13: 0b11; CG14: 0b11; CG15: 0b11 CCM, CCGR1, 0xFFFFCFFF, CG0: 0b11; CG1: 0b11; CG2: 0b11; CG3: 0b11; CG4: 0b11; CG5: 0b11; CG6: 0b00; CG7: 0b11; CG8: 0b11; CG9: 0b11; CG10: 0b11; CG11: 0b11; CG12: 0b11; CG13: 0b11; CG14: 0b11; CG15: 0b11 CCM, CCGR2, 0xFFFFFFFF, CG0: 0b11; CG1: 0b11; CG2: 0b11; CG3: 0b11; CG4: 0b11; CG5: 0b11; CG6: 0b11; CG7: 0b11; CG8: 0b11; CG9: 0b11; CG10: 0b11; CG11: 0b11; CG12: 0b11; CG13: 0b11; CG14: 0b11; CG15: 0b11 CCM, CCGR3, 0xFFFFFFFF, CG0: 0b11; CG1: 0b11; CG2: 0b11; CG3: 0b11; CG4: 0b11; CG5: 0b11; CG6: 0b11; CG7: 0b11; CG8: 0b11; CG9: 0b11; CG10: 0b11; CG11: 0b11; CG12: 0b11; CG13: 0b11; CG14: 0b11; CG15: 0b11 CCM, CCGR4, 0xFFFFFFFF, CG0: 0b11; CG1: 0b11; CG2: 0b11; CG3: 0b11; CG4: 0b11; CG5: 0b11; CG6: 0b11; CG7: 0b11; CG8: 0b11; CG9: 0b11; CG10: 0b11; CG11: 0b11; CG12: 0b11; CG13: 0b11; CG14: 0b11; CG15: 0b11 CCM, CCGR5, 0xFFFFFFFF, CG0: 0b11; CG1: 0b11; CG2: 0b11; CG3: 0b11; CG4: 0b11; CG5: 0b11; CG6: 0b11; CG7: 0b11; CG8: 0b11; CG9: 0b11; CG10: 0b11; CG11: 0b11; CG12: 0b11; CG13: 0b11; CG14: 0b11; CG15: 0b11 CCM, CCGR6, 0xFFFFFFFF, CG0: 0b11; CG1: 0b11; CG2: 0b11; CG3: 0b11; CG4: 0b11; CG5: 0b11; CG6: 0b11; CG7: 0b11; CG8: 0b11; CG9: 0b11; CG10: 0b11; CG11: 0b11; CG12: 0b11; CG13: 0b11; CG14: 0b11; CG15: 0b11 CCM, CCGR7, 0xFFFFFFFF, CG0: 0b11; CG1: 0b11; CG2: 0b11; CG3: 0b11; CG4: 0b11; CG5: 0b11; CG6: 0b11 CCM, CMEOR, 0x7FFFFFFF, MOD_EN_OV_GPT: MOD_EN_OV_GPT_1; MOD_EN_OV_PIT: MOD_EN_OV_PIT_1; MOD_EN_USDHC: MOD_EN_USDHC_1; MOD_EN_OV_TRNG: MOD_EN_OV_TRNG_1; MOD_EN_OV_CANFD_CPI: MOD_EN_OV_CANFD_CPI_1; MOD_EN_OV_CAN2_CPI: MOD_EN_OV_CAN2_CPI_1; MOD_EN_OV_CAN1_CPI: MOD_EN_OV_CAN1_CPI_1
So to summarise, it is all working for me, many thanks again.
my understanding is that this is all platform specific boot time configuration which is fine in DT
also worth noting that I expect this is a temporary solution to add more flexibility since Daniel's clock management RFC would probably change all this again
Support configuration of SYSPLL (a fractional-n PLL) on iMXRT parts using devicetree.
This PR also sets up the iMXRT1040 SOC to clock from the SYSPLL, running at 528MHz (the maximum supported frequency for the part)
Fixes #70755