Closed ThreeEights closed 2 weeks ago
@morsisko - Feel free to comment on this issue.
Hello, sorry for late response. When I was designing the driver I was using mainly ESP32 SPI driver. I also encountered bugs described here: https://github.com/zephyrproject-rtos/zephyr/issues/54746
ESP32 driver send bytes as they are in the buffer (so that byte[0] will be sent first on the SPI, then byte[1] and so on). I don't know if it is correct behavior or not, however definitely there needs to be some kind of agreement about the byte order between different SPI drivers.
@morsisko - Thanks. I think I have the Pico PIO SPI driver working that way, too. It seems like a sensible convention: Send the bytes in the order in the buffer, whether sending 8, 16, or 32 bytes in a transaction. Once I have a pull request ready we should be able to close this issue.
This issue has been marked as stale because it has been open (more than) 60 days with no activity. Remove the stale label or add a comment saying that you would like to have the label removed otherwise this issue will automatically be closed in 14 days. Note, that you can always re-open a closed issue at any time.
@yonsch - Can you remove the "stale" label? The fix for this was supposed to be in 3.7, but didn't get reviewed in time.
This issue has been marked as stale because it has been open (more than) 60 days with no activity. Remove the stale label or add a comment saying that you would like to have the label removed otherwise this issue will automatically be closed in 14 days. Note, that you can always re-open a closed issue at any time.
dismiss stale
Describe the bug The PIO-based SPI driver for the Raspberry Pi Pico (and the RP2040 in general) sends data out the SPI bus in the wrong byte order when SPI_WORD_SET() is 16 or 32 bits, and reverses the byte order of the input data. Data is passed to the SPI driver (tx buffer) in the byte order intended for transmission. However, the little-endian PIO SPI driver treats the data as 16- or 32-bit integers, loading the data into the transmit FIFO in the reverse of the correct order and not correcting the reversed data in the receive FIFO.
To Reproduce Steps to reproduce the behavior:
west build -p auto -b rpi_pico
Observed behavior The command to read the TEST_CONFIG register should be 0x8F000008, but is sent on the bus as 0x08 0x00 0x00 0x8F. The input line receives 0xE0 0x00 0x00 0x8B, but the status message delivered to the application is 0x8B0000E0. The TMAG5170 driver repeats the attempt to read the TEST_CONFIG register, never leaving the driver's init function.
Expected behavior The data should be transmitted in the order provided, regardless of the CPU byte order: 0x8F 0x00 0x00 0x08, and the received data should be placed in the rx buffer in the order expected: 0xE0 0x00 0x00 0x8B.
Impact The PIO SPI driver cannot operate correctly in either SPI_WORD_SET(16) or SPI_WORD_SET(32) configurations.
Logs and console output Data as exchanged on the SPI bus (first two 32-bit exchanges):
Environment (please complete the following information):
Additional context boards/rpi_pico.overlay used to build sample:
TMAG5170 connections to RPI Pico: