Open PeeJay opened 4 weeks ago
@PeeJay Are you able to submit a fix for the wrong CAN module clock? I do not have access to any Atmel SAM based boards.
Will do.
I've now run into another issue while testing - randomly when recieving can packets I'm mostly getting <err> can_mcan: Message RAM access failure
. About 1/8 are received successfully. When I connect the debugger (a Jlink) the error instantly stops. I haven't specifically enabled or disabled the MPU or cache.
Are you able to check under which of these conditions it occurs?
Describe the bug I'm developing a custom same51 board and was failing to can_set_bitrate(). After some googling I found the test suite and ran it on my board, where I discovered the can clock was set to only 4MHz by default (which is next to useless). I discovered the divider in the same5x.dtsi was set to 12, hence the low clockrate. Overriding that in the board config to 1 gives 48 MHz which is much better, but still not ideal.
To Reproduce Run the test
tests/drivers/can/timing
on any same51 boardExpected behavior
Logs and console output Default divider of 12 (4 MHz):
Divider of 1 (48 MHz):
Environment (please complete the following information):