driver: ssp: fix MLCS bits programming

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driver: ssp: fix MLCS bits programming #76299

Closed dnikodem closed 1 month ago

dnikodem commented 2 months ago

Describe the bug

The MLCS field in the SSP driver is programmed with incorrect bits length. The MLCS field length is a 3-bit value, whereas the macro used to program it attempts to modify 4 bits.

It is necessary to modify the macro used to program the MLCS field and the method used to program the link clock source.

To Reproduce

Expected behavior

Impact

Logs and console output

Environment (please complete the following information):

OS: (e.g. Linux, MacOS, Windows)
Toolchain (e.g Zephyr SDK, ...)
Commit SHA or Version used

Additional context

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marc-hb commented 2 months ago

Thanks for filing this. I think you said something important in #76258

In my opinion it is not critical cause probably no one will change the MLCS register value in runtime to select different clock.

Your fix https://github.com/zephyrproject-rtos/zephyr/pull/76258/commits/a5f0b0f65a7345e8d27f669a4a180fa6314f036e should still be merged of course.

dnikodem commented 2 months ago

Fix: https://github.com/zephyrproject-rtos/zephyr/pull/76310 - in review

dnikodem commented 2 months ago

Waiting for CI results : https://github.com/thesofproject/sof/pull/9332

dnikodem commented 1 month ago

Fix is merged: https://github.com/zephyrproject-rtos/zephyr/pull/76310