Sample USB-C Sink Not Working in Zephyr v3.7.0 on weact_stm32g431_core

[recalci]

Describe the bug

After upgrading Zephyr from v3.6.0 to v3.7.0, the project samples/subsys/usb_c/sink fails to work correctly on weact_stm32g431_core. The project compiles successfully, but the USB-C sink functionality does not work as expected.

To Reproduce

Steps to reproduce the behavior:

1. CONFIG_LOG_DEFAULT_LEVEL=3
2. Switch to Zephyr v3.7.0.
3. Run west update to update dependencies.
4. Compile and flash weact_stm32g431_core samples/subsys/usb_c/sink.
5. The project fails to work correctly.

Expected behavior

The project should compile and run successfully, enabling USB-C PD sink functionality.

Environment (please complete the following information):

• OS: Windows 10
• Toolchain: Zephyr SDK 0.16.8
• Commit SHA or Version used: v3.7.0

Additional context

The issue seems to be related to changes in the hal_stm32 module between v3.6.0 and v3.7.0. Specifically, the revision 60c9634f61c697e1c310ec648d33529712806069 works correctly, while f1317150eac951fdd8259337a47cbbc4c2e6d335 does not.

- name: hal_stm32
  revision: f1317150eac951fdd8259337a47cbbc4c2e6d335
  path: modules/hal/stm32
  groups:
    - hal

Using git bisect, the issue was narrowed down to the commit 6d2120588d502e91c33f379728d2ce9a6fa1e9e3.

Additional Information

1. The issue specifically occurs when CONFIG_LOG_DEFAULT_LEVEL=3. At log levels 2 or 4, the version of hal_stm32 does not impact the functionality.

2. When using the problematic version of hal_stm32 with CONFIG_LOG_DEFAULT_LEVEL=3, there is no log output from the UART. This issue does not occur at log levels 2 or 4.

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[marwaiehm-st]

Hi @recalci , Would it be possible for you to share the log of the test with me?

[recalci]

Hi @marwaiehm-st , thanks for responses.

I have gathered some additional information that might be crucial for diagnosing the issue.

1. The problem occurs specifically when CONFIG_LOG_DEFAULT_LEVEL=3. At log levels 2 or 4, the version of hal_stm32 does not impact the functionality.

2. Additionally, when using the problematic version of hal_stm32 with CONFIG_LOG_DEFAULT_LEVEL=3, there is no log output from the UART. This behavior is not observed at other log levels.

I will update the issue with these new details.

Here is the normal log output when everything is functioning correctly:

[00:00:00.000,000] <err> usbc_stack: Couldn't disable vconn: -134
[00:00:00.000,000] <inf> usbc_stack: ErrorRecovery
[00:00:00.000,000] <inf> usbc_stack: Disabled
[00:00:00.000,000] <inf> usbc_stack: PE_SUSPEND
[00:00:00.000,000] <inf> usbc_stack: PRL_HR_SUSPEND
[00:00:00.000,000] <inf> usbc_stack: PRL_TX_SUSPEND
*** Booting Zephyr OS build v3.7.0-1040-g6b7558a9bf96 ***
[00:00:00.000,000] <inf> usbc_stack: ErrorRecovery
[00:00:00.245,000] <inf> usbc_stack: Unattached.SNK
[00:00:00.245,000] <inf> usbc_stack: AttachWait.SNK
[00:00:00.449,000] <inf> usbc_stack: Attached.SNK
[00:00:00.449,000] <inf> usbc_stack: PE_SNK_Startup
[00:00:00.449,000] <inf> usbc_stack: PRL_INIT
[00:00:00.449,000] <inf> usbc_stack: PRL_HR_Wait_for_Request
[00:00:00.449,000] <inf> usbc_stack: PRL_Tx_PHY_Layer_Reset
[00:00:00.449,000] <inf> usbc_stack: PRL_Tx_Wait_for_Message_Request
[00:00:00.449,000] <inf> usbc_stack: PE_SNK_Discovery
[00:00:00.449,000] <inf> usbc_stack: PE_SNK_Wait_For_Capabilities
[00:00:00.470,000] <inf> main: PWR 3A0
[00:00:00.599,000] <inf> usbc_stack: RECV 51a1/5 
[00:00:00.599,000] <inf> usbc_stack:    [0]0801912c 
[00:00:00.599,000] <inf> usbc_stack:    [1]0002d12c 
[00:00:00.599,000] <inf> usbc_stack:    [2]0003c12c 
[00:00:00.599,000] <inf> usbc_stack:    [3]0004b12c 
[00:00:00.599,000] <inf> usbc_stack:    [4]0006412c 
[00:00:00.600,000] <inf> usbc_stack: PE_SNK_Evaluate_Capability
[00:00:00.600,000] <inf> usbc_stack: PE_SNK_Select_Capability
[00:00:00.601,000] <inf> usbc_stack: PRL_Tx_Wait_for_PHY_response
[00:00:00.601,000] <inf> usbc_stack: RECV 01a1/0 
[00:00:00.601,000] <inf> usbc_stack: PRL_Tx_Wait_for_Message_Request
[00:00:00.605,000] <inf> usbc_stack: RECV 03a3/0 
[00:00:00.605,000] <inf> usbc_stack: PE_SNK_Transition_Sink
[00:00:00.716,000] <inf> usbc_stack: RECV 05a6/0 
[00:00:00.716,000] <inf> usbc_stack: PE_SNK_Ready
[00:00:01.000,000] <inf> main: Source Caps:
[00:00:01.000,000] <inf> main: PDO 0:
[00:00:01.000,000] <inf> main:  Type:              FIXED
[00:00:01.000,000] <inf> main:  Current:           3000
[00:00:01.000,000] <inf> main:  Voltage:           5000
[00:00:01.000,000] <inf> main:  Peak Current:      0
[00:00:01.000,000] <inf> main:  Uchunked Support:  0
[00:00:01.000,000] <inf> main:  Dual Role Data:    0
[00:00:01.000,000] <inf> main:  USB Comms:         0
[00:00:01.000,000] <inf> main:  Unconstrained Pwr: 1
[00:00:01.000,000] <inf> main:  USB Suspend:       0
[00:00:01.000,000] <inf> main:  Dual Role Power:   0
[00:00:01.050,000] <inf> main: PDO 1:
[00:00:01.050,000] <inf> main:  Type:              FIXED
[00:00:01.050,000] <inf> main:  Current:           3000
[00:00:01.050,000] <inf> main:  Voltage:           9000
[00:00:01.050,000] <inf> main:  Peak Current:      0
[00:00:01.050,000] <inf> main:  Uchunked Support:  0
[00:00:01.050,000] <inf> main:  Dual Role Data:    0
[00:00:01.050,000] <inf> main:  USB Comms:         0
[00:00:01.050,000] <inf> main:  Unconstrained Pwr: 0
[00:00:01.050,000] <inf> main:  USB Suspend:       0
[00:00:01.050,000] <inf> main:  Dual Role Power:   0
[00:00:01.100,000] <inf> main: PDO 2:
[00:00:01.100,000] <inf> main:  Type:              FIXED
[00:00:01.100,000] <inf> main:  Current:           3000
[00:00:01.100,000] <inf> main:  Voltage:           12000
[00:00:01.100,000] <inf> main:  Peak Current:      0
[00:00:01.100,000] <inf> main:  Uchunked Support:  0
[00:00:01.100,000] <inf> main:  Dual Role Data:    0
[00:00:01.100,000] <inf> main:  USB Comms:         0
[00:00:01.100,000] <inf> main:  Unconstrained Pwr: 0
[00:00:01.100,000] <inf> main:  USB Suspend:       0
[00:00:01.100,000] <inf> main:  Dual Role Power:   0
[00:00:01.151,000] <inf> main: PDO 3:
[00:00:01.151,000] <inf> main:  Type:              FIXED
[00:00:01.151,000] <inf> main:  Current:           3000
[00:00:01.151,000] <inf> main:  Voltage:           15000
[00:00:01.151,000] <inf> main:  Peak Current:      0
[00:00:01.151,000] <inf> main:  Uchunked Support:  0
[00:00:01.151,000] <inf> main:  Dual Role Data:    0
[00:00:01.151,000] <inf> main:  USB Comms:         0
[00:00:01.151,000] <inf> main:  Unconstrained Pwr: 0
[00:00:01.151,000] <inf> main:  USB Suspend:       0
[00:00:01.151,000] <inf> main:  Dual Role Power:   0
[00:00:01.201,000] <inf> main: PDO 4:
[00:00:01.201,000] <inf> main:  Type:              FIXED
[00:00:01.201,000] <inf> main:  Current:           3000
[00:00:01.201,000] <inf> main:  Voltage:           20000
[00:00:01.201,000] <inf> main:  Peak Current:      0
[00:00:01.201,000] <inf> main:  Uchunked Support:  0
[00:00:01.201,000] <inf> main:  Dual Role Data:    0
[00:00:01.201,000] <inf> main:  USB Comms:         0
[00:00:01.201,000] <inf> main:  Unconstrained Pwr: 0
[00:00:01.201,000] <inf> main:  USB Suspend:       0
[00:00:01.201,000] <inf> main:  Dual Role Power:   0

Please let me know if there is anything else I can provide to assist in resolving this issue.

[marwaiehm-st]

Hi @recalci , thank you for the responses.

I reproduced the issue on the board b_g474e_dpow1, but it occurs when CONFIG_LOG_DEFAULT_LEVEL=2.

The regression is due to a modification in the function "LL_SetFlashLatency" on the file "stm32g4xx_ll_utils.c". A condition was added to set the latency based on the BOOST Mode status, but in my case, it's disabled because the HCLKFrequency is 128MHz. According to the clock control, the frequency should be greater than 150MHz to enable the Boost Mode.

I propose, for the moment, to configure the PLL in the overlay of your board "samples/subsys/usb_c/sink/boards/weact_stm32g431_core.overlay" to enable PLL Clock Boost Mode

&clk_hsi {
    status = "okay";
};

&pll {
    div-m = <4>;
    mul-n = <85>;
    div-p = <2>;
    div-q = <2>;
    div-r = <2>;
    clocks = <&clk_hsi>;
    status = "okay";
};

&rcc {
    clocks = <&pll>;
    clock-frequency = <DT_FREQ_M(170)>;
    ahb-prescaler = <1>;
    apb1-prescaler = <1>;
    apb2-prescaler = <1>;
};

Could you please test with this configuration?

[recalci]

@marwaiehm-st I have tested the suggested configuration, and it works. Thank you for your help! I guess this is a temporary solution. Should I close this issue?

[marwaiehm-st]

Hi @recalci No, you should not close this issue until we find a permanent solution.

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