Open GeorgeCGV opened 2 weeks ago
The Bit is actually the 8th of the RCC_AHB3ENR and some stm32h7 devices have not this bit: only stm32H7 dual core devices have. Earlier we took the option to set the bit for all stm32h7 else we should have to identify dual core devices inside the stm32h7. We considered at that time that writing the bit 8 of the RCC_AHB3ENR did not cause any wrong behavior when the bit was not defined.
We can now define the clock property only for stm32h7_dual core mcus and have this clock_on in the stm32h7_flash_init only for the "st,stm32h7-flash-controller" with that clocks property
clocks = <&rcc STM32_CLOCK(AHB3, 8U)>;
Describe the bug A reserved bit at position
8
is being set to1
instatic int stm32h7_flash_init(const struct device *dev)
forRCC_AHB3ENR
register:RCC_AHB3ENR (RM0468 Rev 3)
The clock and bit to set come from
zephyr/dts/arm/st/h7/stm32h7.dtsi
:@erwango maybe the intention was to set
FLASHLPEN
inRCC_AHB3LPENR
? The bit position matches and register containsAHB3
in the name.RCC_AHB3LPENR (RM0468 Rev 3)
To Reproduce
st,stm32h7-flash-controller
driver and observeRCC_AHB3ENR
state.Expected behavior The reserved bit shall not be set.
Environment (please complete the following information):