This puts the syscall helpers into the vector code section, and is a tiny TLB optimization. Before this, worst case scenario is that there would 2 instruction TLB misses when both the syscall helpers and the vector code pages are not in TLB cache. With this change, there would be at most 1 instruction TLB miss as now the syscall helper and the vector code (which includes exception handling code and xtensa_do_syscall()) are now in the same page, and the same TLB entry.
This puts the syscall helpers into the vector code section, and is a tiny TLB optimization. Before this, worst case scenario is that there would 2 instruction TLB misses when both the syscall helpers and the vector code pages are not in TLB cache. With this change, there would be at most 1 instruction TLB miss as now the syscall helper and the vector code (which includes exception handling code and xtensa_do_syscall()) are now in the same page, and the same TLB entry.