"In Risc-v privileged spec section "Guest Physical Address Translation" states that:
The G bit in all G-stage PTEs is reserved for future standard use. Until its use is defined by a standard extension, it should be cleared by software for forward compatibility, and must be ignored by hardware.
I wrote an assertion that states:
If during the second stage translation, the pte.g bit is high then in the next cycle trans_error must be asserted.
Below is the counter-example of the assertion failure. Here translate_pdtp=0, en_1s=1 and en_2s = 1. In the 11th cycle there is the first leaf pte where iosatp is translated, in the 13th cycle there is the second leaf pte where first stage translation happened, and in the 15th cycle, there is a third non-leaf pte for G-Stage translation where pte.g bit is high. Now in the next cycle trans_error must be high because pte.g bit is asserted but here trans_error=0 which is wrong.
"In Risc-v privileged spec section "Guest Physical Address Translation" states that:
I wrote an assertion that states:
Below is the counter-example of the assertion failure. Here
translate_pdtp=0,en_1s=1 anden_2s= 1. In the 11th cycle there is the first leaf pte whereiosatpis translated, in the 13th cycle there is the second leaf pte where first stage translation happened, and in the 15th cycle, there is a third non-leaf pte for G-Stage translation wherepte.gbit is high. Now in the next cycletrans_errormust be high becausepte.gbit is asserted but heretrans_error=0 which is wrong.