Closed xiaowei6911 closed 10 years ago
I'm not sure which project you are referring to.
Also, I don't think the Qsys HPS settings actually affect anything, since we are programming the FPGA after the HPS has already booted.
I am talking about sockit_test-master
Frank Xiao
On Feb 11, 2014, at 3:03 PM, "Howard Mao" notifications@github.com wrote:
I'm not sure which project you are referring to.
Also, I don't think the Qsys HPS settings actually affect anything, since we are programming the FPGA after the HPS has already booted.
— Reply to this email directly or view it on GitHub.
I have no idea. The HPS settings in the QSF file were generated by a script, and they seem to work for me, so I'm not going to question it.
quick questions about the setting in the project: sockit_test-master HPS SDRAM setting: the memory clock and the data path width. I looked at the DDR3 datasheet and it seems the combination of CL=7 and CWL = 6 is not allowed at tck = 3.33ns (300MHz) and the datapath width is 8 in the setting but the schematic shows 32bit. am I using the wrong branch of the project?