I am following your online tutorial blog. I made the qsys system. but as soon as I tried to generate HDL, it is showing me following errors
Error: soc_system.: There are multiple signals with role "export". Components using hw.tcl package 14.0 and greater must specify unique signal roles. while executing"add_interface_port conduit_end slower export Input 1"
Error: soc_system.delay_ctrl_0.avalon_slave_0: Interface must have an associated reset
Error: soc_system.delay_ctrl_0.avalon_slave_0: delay_ctrl_0.avalon_slave_0 must declare an associated reset
I am using quartus 2 version 18. I dont know what is happening. can you please guide me?
I am following your online tutorial blog. I made the qsys system. but as soon as I tried to generate HDL, it is showing me following errors
Error: soc_system.: There are multiple signals with role "export". Components using hw.tcl package 14.0 and greater must specify unique signal roles. while executing"add_interface_port conduit_end slower export Input 1"
Error: soc_system.delay_ctrl_0.avalon_slave_0: Interface must have an associated reset
Error: soc_system.delay_ctrl_0.avalon_slave_0: delay_ctrl_0.avalon_slave_0 must declare an associated reset
I am using quartus 2 version 18. I dont know what is happening. can you please guide me?