search

zherczeg / sljit

Platform independent low-level JIT compiler
Other
843 stars 74 forks source link

loongarch: add memory fence & support tmp register for atomic #263

Closed lrzlin closed 2 months ago

lrzlin commented 2 months ago

Implement LoongArch dbar 0 memory fence, which is a full memory barrier just like fence iorw, iorw on RISC-V.

Also support tmp register for atomic, it worth noticing that TMP_REG2 seems to have collision issues, so I use TMP_REG3 instead.

Done: https://github.com/zherczeg/sljit/issues/262