Open kassane opened 2 years ago
I don't known what would be the relevance of this to the project #4456 itself. But it would help in testing in real and simulated environments of this architecture.
I use a low-cost device based on the T-Head/Alibaba model this CPU is known as D1 (Xuantie C906) and unfortunately does not have mainstream llvm support.
This device supports some extensions beyond baseline_rv64
including 128bit vectorization.
But here comes another internal issue of riscv-v (rvv), because currently devices released before rvv1.0
ratification, have partial support for some drafts (D1 - rvv 0.7.1
support).
@cImport
doesn't support intrinsics afaik (it translates to Zig under the hood)
More importantly, I don't believe that Zig has any way of exposing these operations (at least, not in their full generality), since its vectors are fixed-length. ARM SVE intrinsics have the same problem. This is subject to change as the language evolves, of course.
For more discussion, see: https://github.com/ziglang/zig/issues/7702
Your best bet in the meantime is to try using inline ASM instead.
Your best bet in the meantime is to try using inline ASM instead.
Yes, it is! I was recently looking at but possible solution applied to rustacean and maybe I can replicate this experiment with zig and asm. https://github.com/cryptape/rvv-encoder
--- edit
Another reference
zig cc
master version no build riscv_vector.h
, v0.10.x works.
see: https://godbolt.org/z/6Yacqc1qn
To be clear, is there still a bug here, or should this be closed?
To be clear, is there still a bug here, or should this be closed?
The original issue that translate-c is not seeing the __builtin_rvv_vsetvlimax
builtin function remains. The zig cc
issue of the functions not being found is not a bug, the functions were renamed to prepend with __riscv_
, so __riscv_vsetvlmax_e8m8
. More context: https://github.com/llvm/llvm-project/commit/54b40a1785e9e7602fd69cd274cb46fc5746e029
Zig Version
0.10.0-dev.2981+7090f0471
Steps to Reproduce
I am trying to do some tests with the zig language using riscv vectorization, however both stage1 and stage2 are not supported. Then while using the c-code to perform these tests, but an error occurred!
References RISC-V Vector Extension Intrinsic Document RISC-V Vector extension Spec
Expected Behavior
Works
Actual Behavior
Fail