LLVM signaling NaN gets lowerd to quiet NaN (arm)

[Hardy7cc]

Zig Version

0.11.0-dev.1362+7f604b6f4

Steps to Reproduce and Observed Behavior

Followup from #14272

When compiling the following llvm-ir with llc -mtriple arm-linux-none the constant value 0xH7C01 seems to get turned into #32256 (0x7E00) inverting the signaling bit and discarding the payload of the float value.

define dso_local void @entry() #0 {
Entry:
    %0 = alloca half, align 2
    store half 0xH7C01, ptr %0, align 2
    ret void
}

Generated assembler:

entry:
        sub     sp, sp, #4
        mov     r0, #1
        orr     r0, r0, #32256
        strh    r0, [sp, #2]
        add     sp, sp, #4
        mov     pc, lr

When I examined it with godbolt (https://godbolt.org/z/487zsYsnq) the example is even more weird. The zig example code does switch from 0xH7C01 to #32257 (0x7E01) inverting the signaling bit but preserving the payload.

Expected Behavior

The float constant should not change between llvm-ir and asm. 0xH7C01 should turn into #31745 not #32256 (0x7E00)

[Hardy7cc]

https://github.com/llvm/llvm-project/issues/60130

[alexrp]

The isSignalNan test still fails for arm, aarch64, and powerpc, as well as when using the C backend, but passes everywhere else. The other disabled tests pass everywhere.