Open fengb opened 3 years ago
This is a potential LLVM12 regression, as it had previously worked fine.
// zig build-obj crash.zig -target powerpc-freestanding-eabi export fn sysret(value: u32, errored: bool) void { _ = asm volatile ("rfi" : [ret] "={r3}" (-> usize) : [value] "{r3}" (value), [err] "{cr0}" (errored) // cr0 - cr7 crashes the compiler // cr8 detects as not a real register // rX works just fine ); }
so this works on 0.7.1 and segfaults on 0.8.0 ?
This is a potential LLVM12 regression, as it had previously worked fine.