Enable JTAG support

[jdbaptista]

Making a pinout for the JTAG pins (MTDI, MTDO, etc.) and fixing strapping issues with time delay pullups / pulldowns should enable this. Example circuit (that I think is correct):

When R1 >> R2 and the transistor is closed, Vout = Vin (R2 / (R1 + R2)) ~= 0. When the transistor is open, Vout = Vin. The same idea with a pullup resistor should be even easier, as no voltage divider is necessary.

[jdbaptista]

The following LTSpice circuits show example implementations. Note that the NOT gate in the circuit driving the output low can be replaced with a depletion mode mosfet depletion mode pmos mosfet (on when Vgs is low, off when Vgs is high). Work still needs to be done to determine the proper RC time constants for each circuit and resistor values to make sure the current is not too high.

Drive low during RC charge up using nmos transistor (and not gate):

Drive high during RC charge up using pmos transistor:

[jdbaptista]

The esp32-wroom-32 datasheet specifies a 0ms setup time and 1ms hold time for strapping pins when CHIP_PU/EN goes high (pg. 11). A high level input voltage is defined to be above 0.75 VDD = 0.75 3.3 = 2.475V, and a low level input voltage is defined to be below 0.25 VDD = 0.25 3.3 = 0.825V. Using this n-channel depletion-mode transistor with Vth = -1.5v, ie. 3.3 - 1.5 = 1.8v capacitor charge, a hold of 3ms requires a time delay constant of a little over 3ms, which would charge to 3.3 0.632 = 2.0856 in 3ms. For a 1ms minimum hold time, a 3ms time constant will suffice. This can be achieved with T = R C = 3k * 1u = 3ms. To be safe, the resistor can be set to 5k for a hold time of 5ms.

For driving low, as the low level input voltage is below 0.825V, the resistors should satisfy 0.825 < 3.3 * (R2 / (R3 + R2)). The input device should be able to keep the input voltage above 2.475V at a high logic level, so the voltage drop across R3 must be Vd < 0.825V when R2 is disconnected, which means that the input device must be able to source some current. To avoid this, an op-amp unity gain buffer should be used before the R3/R2 voltage divider. With an op-amp handling current issues, the resistor values can be R3 = 30k and R2 = 5k, which equates to an output voltage of 0.47V.

For driving high, the same RC delay circuit can be used and R2 can be sufficiently high (ie. 30k) to reduce current draw. An op-amp should be used to separate the device from the JTAG driving device.

[jdbaptista]

It turns out that depletion-mode pmos transistors (which is what would be necessary to drive the circuit low) are not common components and it will be better to simply use the inverter as shown in the LTSpice example. this IC contains 2 enhancement mode nmos transistors with a threshold voltage of Vth = 1.0V. The LTSpice graph shows that a 10k, 1u RC combo should satisfy the hold time requirement even at only 1V.

The drive up circuit uses this pmos enhancement mode mosfet, which has a Vth of between -1.1 to -2.1V. In the worst case, the mosfet will turn on after the capacitor charges to just 1.2V, which can still be met with the RC combo above (that is, the hold time is still satisfied).

[jdbaptista]

See commit 56c4915 on issue_7 branch. Any thoughts on the design before I route it?