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zslwyuan / AMF-Placer

AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BRAM...)
Apache License 2.0
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Legalization bugs when cells in a macro are placed across clock region #6

Closed zslwyuan closed 2 years ago

zslwyuan commented 3 years ago

INFO: [DRC 23-27] Running DRC with 8 threads ERROR: [DRC CASC-31] Cascade crosses rbrk: The RAMB36E2 cell design_1_i/DigitRec_0/inst/test_set_V_U/DigitRec_test_set_V_ram_U/ram_reg_bram_11 is cascaded in series to expand the RAMB depth, however the cascade connection crosses a Clock Region. The pin design_1_i/DigitRec_0/inst/test_set_V_U/DigitRec_test_set_V_ram_U/ram_reg_bram_11/CASOREGIMUXA is connected to an ACTIVE net (design_1_i/DigitRec_0/inst/test_set_V_U/DigitRec_test_set_V_ram_U/ram_reg_bram_1_i_1_n_6). This causes a potential hold violation on the dedicated cascade paths between the RAMBs that cannot be corrected. This creates an invalid timing situation. Please take steps to ensure placement of the cascaded RAMB remains inside a single Clock Region or else choose a different implementation style for this RAMB in order to prevent the need for cascading across a Clock Region or the use of this pin. ERROR: [DRC CASC-31] Cascade crosses rbrk: The RAMB36E2 cell design_1_i/DigitRec_0/inst/test_set_V_U/DigitRec_test_set_V_ram_U/ram_reg_bram_11 is cascaded in series to expand the RAMB depth, however the cascade connection crosses a Clock Region. The pin design_1_i/DigitRec_0/inst/test_set_V_U/DigitRec_test_set_V_ram_U/ram_reg_bram_11/CASOREGIMUXEN_A is connected to an ACTIVE net (design_1_i/DigitRec_0/inst/regslice_both_input_V_U/obuf_inst/test_set_V_ce0). This causes a potential hold violation on the dedicated cascade paths between the RAMBs that cannot be corrected. This creates an invalid timing situation. Please take steps to ensure placement of the cascaded RAMB remains inside a single Clock Region or else choose a different implementation style for this RAMB in order to prevent the need for cascading across a Clock Region or the use of this pin. ERROR: [DRC CASC-31] Cascade crosses rbrk: The RAMB36E2 cell design_1_i/DigitRec_0/inst/test_set_V_U/DigitRec_test_set_V_ram_U/ram_reg_bram_9 is cascaded in series to expand the RAMB depth, however the cascade connection crosses a Clock Region. The pin design_1_i/DigitRec_0/inst/test_set_V_U/DigitRec_test_set_V_ram_U/ram_reg_bram_9/CASOREGIMUXA is connected to an ACTIVE net (design_1_i/DigitRec_0/inst/test_set_V_U/DigitRec_test_set_V_ram_U/ram_reg_bram_1_i_1_n_6). This causes a potential hold violation on the dedicated cascade paths between the RAMBs that cannot be corrected. This creates an invalid timing situation. Please take steps to ensure placement of the cascaded RAMB remains inside a single Clock Region or else choose a different implementation style for this RAMB in order to prevent the need for cascading across a Clock Region or the use of this pin. ERROR: [DRC CASC-31] Cascade crosses rbrk: The RAMB36E2 cell design_1_i/DigitRec_0/inst/test_set_V_U/DigitRec_test_set_V_ram_U/ram_reg_bram_9 is cascaded in series to expand the RAMB depth, however the cascade connection crosses a Clock Region. The pin design_1_i/DigitRec_0/inst/test_set_V_U/DigitRec_test_set_V_ram_U/ram_reg_bram_9/CASOREGIMUXEN_A is connected to an ACTIVE net (design_1_i/DigitRec_0/inst/regslice_both_input_V_U/obuf_inst/test_set_V_ce0). This causes a potential hold violation on the dedicated cascade paths between the RAMBs that cannot be corrected. This creates an invalid timing situation. Please take steps to ensure placement of the cascaded RAMB remains inside a single Clock Region or else choose a different implementation style for this RAMB in order to prevent the need for cascading across a Clock Region or the use of this pin. INFO: [Vivado_Tcl 4-198] DRC finished with 4 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. ERROR: [Vivado_Tcl 4-23] Error(s) found during DRC. Placer not run. INFO: [Common 17-83] Releasing license: Implementation 9 Infos, 0 Warnings, 0 Critical Warnings and 5 Errors encountered. place_design failed place_design: Time (s): cpu = 00:00:33 ; elapsed = 00:00:16 . Memory (MB): peak = 12107.438 ; gain = 681.867 ; free physical = 5118 ; free virtual = 26935 ERROR: [Common 17-39] 'place_design' failed due to earlier errors.

while executing

"place_design" (file "/home/tingyuan/Documents/AMF-Placer/build/dumpData_digitRecognition/DumpCLBPacking-first-0.tcl" line 543053)

zslwyuan commented 2 years ago

Problem is fixed in AMF-Placer 2