Decoder and formatter issues

[0xd4d]

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Some instructions should use the address size not the operand size to select the register:

• 67 48 0F01 FC = should use eax, not rax
• 0F01 FC = should use rax, not eax
• 67 48 0F01 D8 = should use eax, not rax
• 0F01 D8 = should use rax, not eax
• there are more similar instructions

vmload doc: "The portion of RAX used to form the address is determined by the effective address size"

clzero doc doesn't say anything about the effective address size but it seems logical that it also uses it.

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EVEX vpblendmd/etc can use {z}

62 F24D9D 64 50 01 = disassembled without {z} 62 F24D9D 65 50 01 = disassembled without {z} 62 F2CD9D 64 50 01 = disassembled without {z} also: vblendmps vblendmpd ...

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62 E30D1B 0A D3 A5 = {sae} is displayed twice

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0F0F CD 97 = pfsqrt should be pfrsqrt 0F0F CD A6 = pfcpit1 should be pfrcpit1

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62 E17C18 2E D3 = missing {sae} 62 E1FD18 2E D3 = missing {sae} 62 E17C18 2F D3 = missing {sae} 62 E1FD18 2F D3 = missing {sae}

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[flobernd]

Thanks for reporting again! I will have a look on wednesday.

[flobernd]

Some instructions should use the address size not the operand size to select the register

clzero/vmload Fixed with https://github.com/zyantific/zydis-db/commit/8d3d5272af45756ced9b927f1bc1be5924ecf68f

there are more similar instructions

Could you please report them as well? Found a few but do not want to miss any.

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EVEX vpblendmd/etc can use {z} {sae} is displayed twice missing {sae}

These ones all seem to be formatter issues - I will look at that later.

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pfsqrt should be pfrsqrt pfcpit1 should be pfrcpit1

We might have picked the wrong mnemonics here. Having a look at the official AMD 3DNOW documentation later.

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I will re-generate the Zydis tables when I'm completely done fixing to avoid too many commits with auto-generated code.

[0xd4d]

Could you please report them as well? Found a few but do not want to miss any.

I'd check all instructions with reg ops that reference memory.