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I've tried using the `asm` tool for riscv32 and riscv64 and it doesn't seem to work correctly.
Example:
```shell
$ asm -c riscv32 'nop'
[!] Could not find system include headers for riscv32-li…
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attached testcase reproduces the following problem on latest from `release/19.x` branch
```
. parser at end of file
2. Code generation
3. Running pass 'Function Pass Manager' on …
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# RISC-V from scratch 2: Hardware layouts, linker scripts, and C runtimes
A post describing how C programs get to the main function. Devicetree layouts, linker scripts, minimal C runtimes, GDB and…
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Motivated by #179 (and #180), I took a look on how the `cortex-m` crate deals with [assembly instructions](https://github.com/rust-embedded/cortex-m/blob/master/cortex-m/src/asm.rs), and most of them …
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Hi,
I'm trying to generate an executable riscv binary (kernel.bin) from a riscv assembly code (kernel.s).
- Using the riscv-none-embed-gcc toolchain, the binary is succesfully generated and I can…
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Hi Tommy,
Thanks for sharing a very good Repo. I am interested to understand how you generated the binaries
[https://github.com/TommyWu-fdgkhdkgh/spike-vp/tree/main/sw](url)
Can you please pro…
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According to the [RISC-V Assembly Programmer's Manual](https://github.com/riscv-non-isa/riscv-asm-manual/blob/main/src/asm-manual.adoc#rvcnorvc), .option norvc is equivalent to .option arch, -c. Howev…
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Hi, I tried running it with just one tile. While there don't appear to be any errors based on the terminal messages, my perf.log file is still empty. Is this expected behavior, or could there be an is…
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I am using RISCV-ISAC to generate the add instruction coverage. I found that some checkpoints in CGF are 0, but it is obvious from the assembly file that this constraint is satisfied. Is this normal?…
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The prior RISC-V ISA Specification (20191213) had a chapter 25, "RISC-V Assembly Programmer’s Handbook" which had a table listing many/most pseudoinstructions. This is no longer present in the most re…