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wsim --sim vcs rv32gc wally32priv
Error on test rv32i_m/privilege/src/WALLY-spi-01.S result 43: adr = 800061bc sim (D$) 000000ff signature = 000000ae
wsim --sim questa rv32gc wally32priv
runs suc…
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I'm trying to add 'fcvt.s.h' testcases in act,Some parameters are as follows
```
inst_1:
// rs1 != rd, rs1==f29, rd==f30,fs1 == 0 and fe1 == 0x0d and fm1 == 0x1b7 and fcsr == 0x0 and rm_val == 7 …
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There's a bunch of new extensions listed in the profile document that are only defined by being mandatory in some profiles that require rv64i. Are these meant to also be legal extensions to other bas…
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~/caravel_board/firmware/mpw2-5/blink$ make clean flash
rm -f *.elf *.hex *.bin *.vvp *.vcd
#/usr/bin/riscv32-unknown-elf-gcc -O0 -march=rv32i_zicsr -Wl,-Bstatic,-T,../sections.lds,--strip-debug -ff…
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I am using riscvOVPsim to run tests, and I encountered the following issue regarding the license expiration:
"Fatal (PER_TMO) Product riscvOVPsim version 20230724.0 license expired on 22 Oct 2023.
P…
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**Describe the bug**
To test the cascade of dependent instructions in 'dep_check', the cost of 'add' in RV32I is modified to 2 by SetCost(2) according to the caption in 'dep_check.c'. However, the te…
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hello
change -march=rv32ixx to -march=rv32i_zicsr in ch32v003
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[rv32i_block_diagram (1).pdf](https://github.com/BrunoLevy/learn-fpga/files/12210764/rv32i_block_diagram.1.pdf)
This block diagram is Right for you?
Carlos
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Currently we need user-provided filters to choose which instructions or sets should (not) be processed by Seal5. See:
```yaml
---
filter:
sets:
drop: [RISCVBase, RISCVEncoding, Zicsr, Zif…