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Hi Ritchie,
I find some errors while compiling the Makefile in "bnn/cpp/accel/sdsoc_build" on the Ubuntu 16.04 system. Here is the log information:
sds++ -sds-pf zed -dmclkid 1 -sds-hw top Accel…
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https://github.com/Xilinx/SDSoC-Tutorials/blob/master/platform-creation-tutorial/Lab2-Creating-Software-Components.md
Step 2: Creating an FSBL Application
3 On the Platform dialog, select Hardwar…
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I'm try to build a point tracker using optical flow example inside the reVision 2018.3 image for zcu104.
I record the flow_x and flow_y variables in to .csv file to better investigation then i real…
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Hi,
can you upload the .tcl file that you have used to create the pfm for the SDSoC platform?
Thanks
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Dear David,
I'm a self driving car researcher of the university of Modena. I'm very interested in your work and I want to test the ZynqNet on Zynq Ultrascale.
I have tested the net with Vivado HLS…
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您好,我在vivado-hls2018.2中复现了这个工程,c仿真和c综合都没有问题,但是在rtl仿真的时候,有以下错误。原因是AXI master 深度不够吗?
// RTL Simulation : "Inter-Transaction Progress" ["Intra-Transaction Progress"] @ "Simulation Time"
////////////////…
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I got that compilation error while trying to build chaidnn using SDSoC v2018.3
Creating Vivado project and starting FPGA synthesis.
What could be the reason of that error ?
WARNING: [VPL…
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Hi, I am using sdsoc to create an accelerator. How can my accelerator on PL can read data from udmabuf ? Thanks !!!
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I follow the project(FFT in SDSoC (C callable IP)) on SDSOC 2017.3, But it complains errors:
ERROR: [XFORM 203-801] Interface mode 'ap_auto' on the actual argument 'fft_status.data.V' (G:/MINO/FPGA/…
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How to evaluate the power consumption of a xfopencv application at SDSoC environment?