dgschwend zynqnet issues

dgschwend / zynqnet

Master Thesis "ZynqNet: An FPGA-Accelerated Embedded Convolutional Neural Network"

GNU General Public License v3.0

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issues

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about ".xdc" file

#71 Candice-Yin opened 3 years ago
0
how to use

#70 jamdodot closed 3 years ago
1
about the result based on petalinux and sdk

#69 ALEX5874 opened 3 years ago
0
The output channel

#68 ALEX5874 opened 3 years ago
0
How to add BN layer

#67 ALEX5874 opened 3 years ago
0
wrong results of the last layer of customized model

#66 mazhongzhong opened 4 years ago
1
Last pooing layer instead of convolution，result is wrong，how to fix it？

#65 biruixing opened 4 years ago
0
Export RTL Error

#64 dldldlfma opened 4 years ago
0
How to run the zynqnet on FPGA?

#63 KrisYoung12 opened 4 years ago
2
Segment fault error == SIGSIVG error

#62 dldldlfma opened 4 years ago
4
why can't the master thesis download? the web display "sorry, this file is invalid so it cannot be displayed"

#61 cverzq opened 4 years ago
1
How to download zynqnet_report.pdf?

#60 CrazybinaryLi closed 4 years ago
0
What does convert_jepg_to_indata_bin.py do?

#59 adki opened 4 years ago
0
what does the (88.38%: class 207 (output 18.94) mean ?

#58 yaw2009 opened 5 years ago
3
synthesis failed

#57 massbhagi opened 5 years ago
0
Inference error, kernel panic Oops: 5 [#1] PREEMPT SMP ARM

#56 tuanho27 closed 5 years ago
0
Synthesizability check failed

#55 mpFPGA opened 6 years ago
0
Error in C Simulation & Synthesis on vivado_hls 2018.2

#54 ysdagar opened 6 years ago
3
Implementation of ZynqNet in ZCU102

#53 rjb95 closed 6 years ago
0
use modified model of zynqnet and run on CPU but segment fault.

#52 KingOfBanana opened 6 years ago
1
About how to generate zynqnet_200M.bit

#51 YzwWh9327 opened 6 years ago
0
Compressing zynqnet

#50 ghost opened 6 years ago
2
Error when running the Train_Caffenet.sh

#49 ghost closed 6 years ago
6
configure the clock rate

#48 denghp5 opened 6 years ago
3
About the Linux Operating System on board

#47 JackChenofNCP closed 6 years ago
2
How to run the project on FPGA?

#46 wangj346 opened 6 years ago
3
something about codes

#45 leeeexp opened 6 years ago
1
Can we train your model for zynqnet on any supercomputer cluster with Digits installed on it? What do you suggest?

#44 ghost closed 6 years ago
2
Questions about the results of output on FPGA

#43 lishen565 opened 6 years ago
29
How to debug/run the C project “zynqnet_sdk” in Xilinx SDK？

#42 lishen565 opened 6 years ago
12
Problems about C cimulation and ZYNQ Board

#41 JackChenofNCP opened 6 years ago
5
Another ZYNQ board

#40 JackChenofNCP closed 6 years ago
0
how to use the unittests codes in the hls?

#39 leeeexp opened 6 years ago
2
how to use the log in hls

#38 leeeexp opened 6 years ago
1
input_offset and weight offsets

#37 ysdagar opened 6 years ago
1
Convert jpeg to binary

#36 snxoxopy opened 6 years ago
4
HLS Synthesis Errors & Warnings

#35 haroonrl opened 6 years ago
2
Is DMA needed?

#34 yaohuFCS closed 6 years ago
2
Create the SDK Project

#33 toniomtb opened 6 years ago
1
Problem in generating bitstream with Vivado SDSOC

#32 HeroGian opened 6 years ago
6
Image Pixel Values Range

#31 wasim6691 opened 6 years ago
8
Problem in exporting RTL in VHLS.

#30 lishen565 opened 6 years ago
36
zynqnet on xilinx XC7Z020

#29 ortalik opened 6 years ago
4
Problem in running C simuliation.

#28 lishen565 closed 6 years ago
4
DEBUGGING the Code

#27 wasim6691 closed 6 years ago
3
"OPMODE Input Warning" Discussion

#26 chengsonghust opened 6 years ago
2
input image for simulation

#25 gueyezizaaa opened 6 years ago
3
Can zynqnet run on xilinx zcu102?

#24 lishen565 opened 6 years ago
7
What's reg(T x) template's pipelining directive working for ?

#23 chengsonghust opened 6 years ago
1
about how to open the project

#22 wswsamao opened 6 years ago
3