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Hi, currently testing stuff with the following config :
AXI4 64 bits -> digilent nexys video DDR (16 bits physical, 128 bits access bus)
Things seems to mess up between lower and upper 64 bits of…
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Hi every one,
I ported rvfpga to nexys video board. I can program FPGA by vscode platformio and LEDs blinks 3 times. So the risc-v is alive.
The platformio.ini is:
```
[env:swervolf_nexys]
pl…
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I am trying to set up Ethernet on the [AC701 development board](https://www.xilinx.com/products/boards-and-kits/ek-a7-ac701-g.html) which uses the [Marvell 88E1116R](https://www.marvell.com/content/da…
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Hi, I'm currently working on a final project for my Verilog class that outputs to a VGA monitor. I already have a basic VGA signal generator module that outputs 640x480, but I don't want to keep gener…
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https://github.com/enjoy-digital/litex/blob/2f5481dbb9ff22cff03f21e8e7d418442b778908/litex_setup.py#L353
```
/usr/lib/gcc-cross/riscv64-linux-gnu/11/../../../../riscv64-linux-gnu/bin/ld: ../libc/l…
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@oliviergoulet5 - can you post this today on the OpenHW Website under news? I tried to submit to the news page but it will only let me "create" but not submit for posting. i'm traveling in Europe and…
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I have run linux on nexys video follow this repo， Now， I want to debug RISC-V boot。
can you give me some suggestion?
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In commit `3ab7eaa` to master branch of LiteX, a flag was removed which causes our build to fail. It works on commits prior to that one. This is the error that is given when we try to run `make`.
```…
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Can opentitan nexys video FPGA work with Eclipse for debugging or trace code in openocd/GDB?
If yes, do I need specific JTGG cable or something like that ?
Thanks a lot.
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Under the vivado 2018.2 env, it occurred error when i run
`make CONFIG=rocket64b2 BOARD=nexys-video bitstream`
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