enjoy-digital litex issues

enjoy-digital / litex

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issues

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cores/cpu/vexiiriscv: Add PMP support

#2130 Dolu1990 opened 4 hours ago
0
liblitespi: add 4k erase function

#2129 m-byte opened 13 hours ago
0
Add efinix SEU interface

#2128 m-byte opened 13 hours ago
0
Fix vdb path for Efinity 2024.2

#2127 m-byte opened 5 days ago
0
No compatibility with Efinity 2024.2.294

#2126 m-byte opened 6 days ago
0
build/lattice/common.py: added Tristate support for ECP5 when build with diamond

#2125 trabucayre closed 1 week ago
1
SPI "Manual Operation useful for Bulk transfers" seems to do nothing

#2124 YusufCelik opened 2 weeks ago
1
build/vhd2v_converter.py: allows users to pass a list of libraries files to compile before convert HDL.

#2123 trabucayre closed 2 weeks ago
1
feat: add uart_with_dynamic_baudrate to SoCCore

#2122 jwise closed 1 week ago
0
CVA6 + Nexys4 DDR - RAM access issues

#2121 juanschroeder opened 2 weeks ago
0
Fixes: Fix not close trace file when the sim is finished

#2120 juiceRv closed 2 weeks ago
2
Utilizing all available CPU cores in the software make cmd

#2119 long-pham closed 2 weeks ago
1
Add FTDI serial number option to openfpgaloader

#2118 long-pham closed 2 weeks ago
1
Use MMCME4_ADV in USPMMCM to enable finer-grained clock output ctrl

#2117 long-pham closed 2 weeks ago
1
Add "--depth" and "-b" arguments for git clone command

#2116 John-Tito opened 2 weeks ago
0
Fix SOC region range check

#2115 CKeilbar closed 2 weeks ago
0
SoC range check boundary issue

#2114 CKeilbar closed 2 weeks ago
0
litex/build/lattice/diamond, platform: allows users to add custom sdc files

#2113 trabucayre closed 3 weeks ago
1
Video-terminal has useable Funtion?

#2112 2jack5657 opened 3 weeks ago
0
Optimize Build, Enhance Clock Control, and add FTDI serial number option to openfpgaloader

#2111 long-pham opened 3 weeks ago
1
litex_sim hangs when adding a call to a function in libliteeth

#2110 jersey99 opened 3 weeks ago
0
Implementing reset comming from the CPU jtag

#2109 Dolu1990 opened 4 weeks ago
0
Stuck at "liftoff" when I try romboot

#2108 Stars-Collector opened 1 month ago
0
Cant have multiple Instances of Custom VHDL core

#2107 Haron123 opened 1 month ago
1
bios: add flash_transfer_cmd

#2106 cklarhorst opened 1 month ago
0
build: io: add multibit/bus variants of SDR and DDR

#2105 maass-hamburg opened 1 month ago
5
Fixes #2103: calculate memory depth for WS2812

#2104 andelf closed 4 weeks ago
1
Unable to create WS2812 of nleds = 1

#2103 andelf closed 4 weeks ago
0
Vexiiriscv update

#2102 Dolu1990 closed 4 weeks ago
1
bios: litespi: clear rx queue after write Beta

#2101 maass-hamburg closed 1 week ago
1
efinix: gpio: use constant output option

#2100 maass-hamburg closed 1 week ago
2
vexiiriscv: add options and conditions

#2099 maass-hamburg closed 1 month ago
5
Add initial uRV CPU support.

#2098 enjoy-digital closed 1 month ago
0
Build diamond addition

#2097 trabucayre closed 4 weeks ago
1
UartLite as a separate module.

#2096 mohammadshahidzade opened 1 month ago
2
soc/cores/cpu/zynqmp/core.py: added support for SGMII via PL with optional PTP support

#2095 trabucayre closed 1 month ago
1
Using irq_setie(1) messes normal programm execution on vexriscv

#2094 Haron123 closed 1 month ago
1
Fixes #2092: provides support for riscv gcc installation on Alpine Linux.

#2093 mgaggero closed 1 month ago
1
litex_setup.py does not install riscv gcc on Alpine Linux

#2092 mgaggero closed 1 month ago
0
Generated Verilog project can't work

#2091 snowprogrammer opened 1 month ago
2
build: efinix: use ifacewriter to set bank voltage

#2090 maass-hamburg closed 1 month ago
1
build: efinix: Tristate fix

#2089 maass-hamburg closed 1 month ago
2
video console

#2088 uglyoldbob closed 3 weeks ago
2
build: efinix: allow clk inverting and different in clk on reg tristates

#2087 maass-hamburg opened 1 month ago
0
build: io: don't use mutable object as default value

#2086 maass-hamburg closed 1 month ago
1
RFC: Etherbone address detection

#2085 m-byte opened 1 month ago
2
Simulate SoC and communicate through UART

#2084 Leopard777 opened 1 month ago
3
build: efinix: EfinixTristateImpl: use GPIO Bus

#2083 maass-hamburg closed 2 months ago
1
Efinix iface signal names.

#2082 enjoy-digital closed 2 months ago
0
build: efinix: common.py; add `SDRInput`

#2081 maass-hamburg closed 2 months ago
4