enjoy-digital litex issues

enjoy-digital / litex

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issues

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Wishbone DMA: Split add_csr() method in add_ctrl()/add_csr().

#2004 enjoy-digital closed 2 days ago
0
integration/soc/add_ethernet: Use separates TX/RX buses/regions for e…

#2003 enjoy-digital closed 3 days ago
0
[RFC] CSRBone or some MMIO debugging bridge

#2002 FlyGoat opened 4 days ago
0
liblitespi: fix xor-used-as-pow bug

#2001 rtucker85 closed 5 days ago
1
AXIDownConverter behaviour on sub-word accesses

#2000 FlyGoat opened 5 days ago
2
csr_bus: Honour re signal from the upstream bus

#1999 FlyGoat closed 4 days ago
1
soc/integration/soc.py: Fix creation of AHB2Wishbone bridge

#1998 FlyGoat closed 5 days ago
1
integration/soc: data_width_convert: Inherit more bus properties

#1997 FlyGoat closed 5 days ago
1
core: add watchdog feature

#1996 maass-hamburg closed 4 days ago
1
soc: add_spi_master: make spi_clk_freq an int

#1995 maass-hamburg closed 1 week ago
1
soc/cores/cpu/zynqmp/core.py: added csr into mem_map, added M_AXI_HPM0_FPD by default

#1994 trabucayre closed 1 week ago
1
Expand litex_sim JTAG support to more CPUs

#1993 FlyGoat closed 6 days ago
2
integration/export: Fix MockCSRRegion base definition.

#1992 AndrewD closed 1 week ago
1
Add json excludes

#1991 AndrewD closed 1 week ago
1
Initial MIPS CPUs support

#1990 FlyGoat opened 1 week ago
2
Fix AXI version of the Zynq7000 busses and add mapped connect fuction

#1989 JoyBed opened 1 week ago
4
Creating a Vagrantfile for LiteX

#1988 ohault opened 1 week ago
1
migen/LiteX generates code which disconnects LED outputs in yosys

#1987 hansfbaier opened 2 weeks ago
2
fatal error: json-c/json.h: No such file or directory when using `litex_sim --cpu-type=vexriscv`

#1986 wojtess closed 2 weeks ago
2
soc.py: Add spi master and changes in litex_json2dts_zephyr.py for the spi drivers

#1985 maass-hamburg closed 2 weeks ago
1
litex_json2renode.py: add option for elf bios file and correct vexriscv variants

#1984 maass-hamburg closed 2 weeks ago
1
linux dts: add vexii clint support

#1983 Dolu1990 closed 2 weeks ago
5
Generate compile_commands.json for Improved Language Server Support

#1982 StoneLin0708 opened 2 weeks ago
2
Console Freezing Issue with CVA5 CPU

#1981 Liamfeng opened 3 weeks ago
1
no STB or CYC when reading from a 8 bit wishbone peripheral using picorv32

#1980 dwalton65 opened 3 weeks ago
1
Proposal: Generate csr offset header files

#1979 AndrewD opened 3 weeks ago
1
soc/integration/builder: use output_dir for csr

#1978 AndrewD closed 2 weeks ago
6
litex_setup installs python packages as --editable, breaking VS Code

#1977 vvuk opened 4 weeks ago
0
Arty A7-100T Boot Linux Panic about irqchip.

#1976 Comet959 opened 4 weeks ago
11
DTS target integration

#1975 AndrewD opened 1 month ago
5
DTS zephyr updates

#1974 AndrewD opened 1 month ago
2
Dts schema compliance

#1973 AndrewD closed 1 month ago
6
tools/litex_json2dts_linux: add all soc sys_clk

#1972 AndrewD closed 1 month ago
1
efinix: add synthesis options to a dictionary in the EfinityToolchain

#1971 jwise opened 1 month ago
2
OpenOCD error when "make" after "./configure --enable-ftdi"

#1970 angerpro1411 opened 1 month ago
3
ci: Build/Install GHDL from sources.

#1969 enjoy-digital closed 1 month ago
0
liblitespi: Fix #1967

#1968 m-byte closed 1 month ago
1
bios: #1953 breaks bios when spiflash is configured "with_master=True"

#1967 m-byte closed 1 month ago
0
litex_json2dts_zephyr.py: include cpu

#1966 maass-hamburg closed 1 month ago
1
ulx3s ecp5 soc not working when using Lattice Diamond

#1965 dwalton65 opened 1 month ago
10
efinix: be able to specify TX_OUTPUT_LOAD on a LVDS PHY on Trion

#1964 jwise closed 1 month ago
1
Running bare-metal firmware on latest CVA5 core

#1963 Rajnesh28 opened 1 month ago
1
Add support for the Efinix reconfiguration interface

#1962 m-byte closed 1 month ago
0
litex_json2dts_zephyr.py: include ctrl

#1961 maass-hamburg closed 1 month ago
1
RFC: refactor devicetree (DTS) generation (draft)

#1960 AndrewD opened 1 month ago
4
Add dynamic mux for UARTBone / normal UART

#1959 jwise opened 1 month ago
0
Simple mistake fix

#1958 nrndda closed 1 month ago
1
Update to Wiki tutorial Page

#1957 yathAg closed 1 month ago
1
Zynqmp aximaster eth i2c uart

#1956 trabucayre closed 1 month ago
1
cores/cpu/naxriscv: fix 64 bits IRQ support

#1955 Dolu1990 closed 1 month ago
1