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VSEARCH could be adapted to run on [RISC-V](https://en.wikipedia.org/wiki/RISC-V) systems. The SIMD code would need to be translated to the vector capabilities of this platform.
Until we have actua…
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I noticed this when dealing with this:
- https://github.com/riscv-collab/riscv-openocd/issues/1098
The Spike targets for debugging use different ISAs/architecture specifications:
- https://gi…
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Godbolts:
https://godbolt.org/z/Tzcb8f4vz
https://godbolt.org/z/YPohsdEso
```
clang: error: unsupported argument 'rocket' to option '-mcpu='
clang: error: unsupported argument 'generic' to opt…
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The [xPack RISC-V Embedded GCC](https://xpack-dev-tools.github.io/riscv-none-elf-gcc-xpack/) toolchain uses the `riscv-none-elf` triplet.
If you agree, I would like to contribute a small pull reque…
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Hello Team,
We've tried to build the NCNN Framework on our RISC-V Development Platform, Where we're seeing the Yolo v5 Example Test Application is providing approximate test prediction values on …
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Hi there
I would be interested to compile bsnes to a RISC V machine.
Do you have any plans to support that platform?
It's an open source architecture, backed by nearly everyone, except ARM…
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### What happened?
Bug: Can't build vulkan backend on RISC-V platform anymore
### Name and Version
git clone https://github.com/ggerganov/llama.cpp.git
cd llama.cpp
apt-get install cmake
cmake -…
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Hi, RISC-V is gaining traction, and more and more powerfull open IP CPUs are becomming available on the market, I was wondering if you guys considered adding RISC-V support for RandomX into `xmrig`.
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I want SecureBoot on RISC-V, that's all.
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According to the [RISC-V Assembly Programmer's Manual](https://github.com/riscv-non-isa/riscv-asm-manual/blob/main/src/asm-manual.adoc#rvcnorvc), .option norvc is equivalent to .option arch, -c. Howev…