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Hi, I would like to test my RISCV project. Till now, in ISA directory, I managed to obtain executable and .dump files for my RV32I machine. There is any possibility to obtain also .hex file?
Does so…
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I am trying to generate a new runtime using the bb-repository with the following command:
`./build_rts.py --output=temp --force --build rv32i`
However I get an error I cannot manage to solve:
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I noticed the following is unused code. If the lower 2 bits of any opcode != 2'b11 then the instruction is a Compressed Instruction and should cause a trap if you don't support Compressed Instructio…
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I'm trying to build the GCC Toolcahin from source since the pre-built toolchain isn't compatible with my OS (I'm on RHEL 7) but I can't seem to get the configure options right.
Something in my hex …
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通过自己编译riscv-gnu-toolchain，命令行如下：
```
make clean
./configure --prefix=$RISCV --enable-multilib --with-cmodel=medany
make -j8
```
riscv-gnu-toolchain:
https://github.com/linsinan1995/riscv-gnu-…
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Hi @aadomn,
Recalling [this observation](https://github.com/RustCrypto/block-ciphers/pull/184) and [your paper](https://eprint.iacr.org/2020/1123.pdf), specifically Figure 6 and the following parag…
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Code cleanup to meet coding conventions.
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If Zvamo implies A extension, rv32i_zvamo is a valid combination. Zvamo will turn on ‘A’ extension implicitly.
If Zvamo does not imply A extension, users need to specify rv32ia_zvamo to support Zvamo…
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when I run this command , it gets some errors. make clean simulate verify postverify XLEN=32 RISCV_DEVICE=I
It shows 'src/JALR-01.S:31: Error: unrecognized opcode `csrw mepc,t0', extension `zicsr' re…
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The command to generate floating point assembly tests in the fadd.d_b1-01.S file[https://github.com/riscv-non-isa/riscv-arch-test/blob/main/riscv-test-suite/rv32i_m/D/src/fadd.d_b1-01.S](https://githu…