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physical-computation
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Sail-RV32I-common
Common files for the Sail RISC-V processor.
MIT License
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Add verilator simulation
#28
theo-brown
opened
3 years ago
0
Look into simplifying data memory
#27
rjlv2
opened
5 years ago
0
JALR might not be compliant with specifications.
#26
rjlv2
opened
5 years ago
0
Possible hazard in combinational logic of control unit
#25
rjlv2
opened
5 years ago
1
Forwarding Unit might not actually require ternary operators.
#24
rjlv2
opened
5 years ago
0
Fixed error in multiplexer select signal logic
#23
rjlv2
closed
5 years ago
0
Simplified data memory. Now it is an array of single words
#22
phillipstanleymarbell
closed
5 years ago
0
Modified data memory
#21
btsouts
opened
5 years ago
0
Initial pass at getting implementation to adhere to our Verilog coding conventions
#20
phillipstanleymarbell
closed
5 years ago
1
Code cleanup to meet coding conventions
#12
phillipstanleymarbell
opened
5 years ago
3
Create LICENSE
#11
rjlv2
closed
5 years ago
0
Possible timing issue
#10
rjlv2
closed
5 years ago
1
Remove trailing whitespace
#9
harrysarson
closed
5 years ago
0
CSR forwarding bug
#8
rjlv2
opened
5 years ago
1
Update readme
#7
rjlv2
closed
5 years ago
1
Further work on CSR
#6
rjlv2
closed
5 years ago
1
LICENCE
#5
harrysarson
closed
5 years ago
1
Update readme
#4
harrysarson
closed
5 years ago
1
Remove trailing whitespace
#3
harrysarson
closed
5 years ago
2
Merge RV32_I and narvie's cpu.v
#2
harrysarson
opened
5 years ago
0
Filter non common files
#1
harrysarson
closed
5 years ago
0
Instruction memory uses LC
#13
harrysarson
opened
5 years ago
1
Implement a modified Harvard architecture, with separate instruction and data caches but single memory.
#15
rjlv2
opened
5 years ago
1
Check branch predictor state machine
#19
rjlv2
closed
5 years ago
1
Implement CSR
#18
rjlv2
opened
5 years ago
2
Look into bottleneck in memory access
#17
rjlv2
closed
5 years ago
1
Differentiate CSRR instructions from ECALL/EBREAK
#16
rjlv2
opened
5 years ago
0