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Hello,
When I was running the test code DATA_TRANSFER, I wanted to change the read file to another place and change the size of the read file. I found that the size created in the test example was:…
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hi, i wanna know is that possible to make xclbin file in vitis?
and how can i config files in vitis 2020.2.
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in sdaccel.ini
xclbin_programing=false
This trigger 2 panics
[ 463.705341] BUG: unable to handle kernel NULL pointer dereference at 0000000000000018
[ 463.706052] IP: [] xocl_create_bo_ioctl…
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I started a f1.2xlarge AWS instance and compiled Array the code per the build instructions. It looked like there might be some additional steps to compiling for an FPGA in the ArrayFire/xilinx_demo r…
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Hi,
I use vitis, vivado 2020.2 for U50 accelerator, provided by xilinx.
INFO: [v++ 60-1454] Run Directory: /home/iiitb/Accelerated_Algorithmic_Trading/build/_x/link/run_link
****** vpl v2020.…
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Thanks for the great repo. I just wanted to see if there is an effort to support edge platforms such as ZCU102?
I am currently working on it, but I am not sure to start. I have already changed the `c…
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I believe there may be a bug running [this specific application](https://github.com/pfsi/tgp_doubler), which is meant to double the property of all vertices (via edge properties).
When executing a …
pf-un updated
3 years ago
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I’m curious why `sh -c` is used to run emulation and hardware execution in SDACCEL flow. It might be useful for the execution issue I have in Vitis. Thanks!
https://github.com/cucapra/polyphemus/bl…
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Hi,
I use vitis, vivado 2020.2 for U50 accelerator, provided by xilinx.
INFO: [v++ 60-1454] Run Directory: /home/iiitb/Accelerated_Algorithmic_Trading/build/_x/link/run_link
****** vpl v2020.…
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