Xilinx SDAccel_Examples issues

Xilinx / SDAccel_Examples

SDAccel Examples

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Update and rename catalog_2017.1.json to catalog_2018.3.json

#61 DatawalletInvestment opened 2 years ago
0
synth ERROR in U50 AAT design

#60 saimt2019507 closed 3 years ago
1
EDGE_COMMON_SW variable is not set

#59 jrjbertram closed 4 years ago
3
hbm_bandwidth on U280 error design does not meet timing

#58 smosanu closed 4 years ago
1
Unable to run VADD RTL kernel Example

#57 ramshankar1990 closed 4 years ago
1
Host streaming example for OpenCL

#56 scarlehoff closed 4 years ago
2
It's err'unable to issue xclExecBuf' when I test the example "hbm_bandwidth" on card u50

#55 xiaoliang201188 closed 4 years ago
1
Not able to build rtl examples

#54 saitej25 closed 4 years ago
8
How to connect DDR4 to RTL Kernel

#53 saitej25 closed 5 years ago
1
how to generate waveform in example SDAccel_Examples/getting_started/rtl_kernel/rtl_vadd

#52 saitej25 closed 5 years ago
1
Using 4 ddr banks in rtl kernel in Sdaccel 2019.1 on Alevo U200

#51 lhh1389 closed 5 years ago
1
Issues when installing SHA on aws FPGA

#50 xcwanAndy closed 4 years ago
3
hw_emu profiled data is different with hw in example "too_many_cu_c"

#49 xiaoliang201188 closed 5 years ago
4
Merge pull request #1 from Xilinx/master

#48 AsimMerchant closed 5 years ago
0
how to generate waveform in example "getting_started/kernel_gmem/burst_rw_c" ?

#47 xiaoliang201188 closed 5 years ago
4
supported failing examples for AWS F1

#46 rajatsarkari closed 5 years ago
0
supported failing examples for AWS F1 DSA

#45 rajatsarkari closed 5 years ago
0
dataflow_subfunc_ocl example and dataflow pragma

#44 salehjg closed 5 years ago
1
How to give user defined input sequences for alignment?

#43 rajumanukonda closed 4 years ago
9
possible bug in "Systolic Arrays (CL)" example

#42 salehjg closed 5 years ago
1
Issues with Using printf() to Debug Kernels

#41 ArmenLevoni closed 5 years ago
1
the application hangs on s_axi_control write transaction

#40 yangensh closed 5 years ago
1
XOCC crash

#39 ted-xie closed 5 years ago
4
Runtime include errors

#38 definelicht closed 5 years ago
4
Update Makefile

#37 JoyceLi-Xilinx closed 5 years ago
1
Using Multiple DDRs

#36 aeeshms closed 5 years ago
3
Fix AES implementation; code cleanup.

#35 nacl closed 6 years ago
1
AES implementation should use a column-major state matrix

#34 nacl closed 6 years ago
0
Merge pull request #1 from Xilinx/master

#33 AsimMerchant closed 6 years ago
0
Error hw_emu.

#32 ramonn76 closed 6 years ago
4
2017.1.RTE not availble after following the tutorial (Create, configure and test an AWS F1 instance)

#31 mkhaled87 closed 6 years ago
7
Failed to Run example: helloworld_ocl

#30 YaoYuxin closed 6 years ago
0
Kernel optimization

#29 hqjenny closed 6 years ago
0
a lapse

#28 lyons-zhang closed 6 years ago
1
a lapse

#27 lyons-zhang closed 6 years ago
2
Can I apply it on SDSoc based on ZCU102

#26 kouyss closed 6 years ago
4
Child process did not launch

#25 Rpona closed 6 years ago
5
GUI on F1

#24 ghost closed 6 years ago
1
Cannot upgrade to invalid target ''

#23 inthesunxkz closed 6 years ago
3
"no HwEm HAL handle" error when executing hardware emulation

#22 troore closed 7 years ago
2
Communication between SLRs

#21 troore closed 6 years ago
2
Failed to Run Examples

#20 zainryan closed 7 years ago
6
Verification of gemm fails

#19 definelicht closed 7 years ago
9
clEnqueueWriteBuffer() cause DMA deadlock when transfering large dataset

#18 doonny closed 7 years ago
5
getting_started

#17 xlnx-jhwang closed 7 years ago
0
not support multiple devices in the platform

#16 alare closed 7 years ago
4
Changing Vadd and README.me with a ull tutorial on text and video

#15 Guilhermeslucas closed 7 years ago
0
Suggestion to improve EoU of the current makefiles in order to provide the customers more flexibility and guidences

#14 sergeisxilinx closed 7 years ago
3
Update rules.mk

#13 sergeisxilinx closed 7 years ago
1
xbinst support in Makefile

#12 heeranand closed 7 years ago
2