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It seems like the IO library is not being built in CI?
https://github.com/RTimothyEdwards/open_pdks/blob/5f6daa1abdc7acd274c5484682496ba16fe182e3/.github/workflows/ci.yml#L15-L21
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It seems like the [`docs/rules/layers/table-c4b-layer-description.csv`](https://github.com/google/skywater-pdk/blob/master/docs/rules/layers/table-c4b-layer-description.csv) file should be split into …
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The simulation of synthesized netlist is always XXX. as shown in the image.
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# FPGAs Are Magic I
> Any sufficiently advanced technology is indistinguishable from magic.
> - Arthur C. Clark
FPGAs are *magic*.
On my Twitter account, I have been posting diagrams of the …
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The flash build space is currently empty, only a placeholder is currently provided.
The components of flash build space will be released at a future date.
Before these files are released access …
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## Expected Behavior
The .lef file should load without any issue on Innovus.
## Actual Behavior
I am getting an error on Innovus when loading the .tlef file (_skywater-pdk/libraries/sky130_fd_sc_…
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## Expected Behavior
According to https://skywater-pdk.readthedocs.io/en/latest/rules/periphery.html#via it says that Min and Max W and L must be 0.150u
## Actual Behavior
Magic does not give any …
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The Verilog-A model does a manual integration of the filament thickness here:
https://github.com/google/skywater-pdk-libs-sky130_fd_pr_reram/blob/6574676cbbd062d63be0f090013d59ced7302349/cells/rera…
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The SRAM build space is currently empty, only a placeholder is currently provided.
The components of the SRAM build space (compatible with OpenRAM) will be released at a future date.
Before thes…
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It looks like OpenFPGA is already using Sphinx for it's documentation. There are a number of extensions that the SymbiFlow project and Antmicro have been working on to make Sphinx documentation for ha…