The-OpenROAD-Project OpenLane issues

The-OpenROAD-Project / OpenLane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

https://openlane.readthedocs.io/

Apache License 2.0

1.25k stars 365 forks source link

issues

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Add docker upgrade instructions to docs

#2132 kareefardi closed 6 hours ago
0
Fix missing values in final metrics generated

#2131 kareefardi opened 1 day ago
0
[ERROR GRT-0118] Routing congestion too high.

#2130 Sanchit-Gupta10 opened 2 days ago
10
Issue with installation of OpenLane, while running make cmd "Error: Command '['/home/HP/OpenLane/venv/bin/python3', '-Im', 'ensurepip', '--upgrade', '--default-pip']' returned non-zero exit status 1."

#2129 WrathofBhuvan11 opened 4 days ago
1
Add MAC with XQuartz case branch on using GUIs section.

#2127 jun1okamura closed 4 weeks ago
0
Remove LEC

#2126 donn closed 1 month ago
0
Power in metrics.csv doesn't match with power in multi_corner_sta.power

#2125 Lukemagik opened 1 month ago
0
Yosys ABC Tool crashes with exit code 139

#2124 Fabbboy opened 1 month ago
6
Error: multi_corner.tcl line 43

#2123 fazliemre opened 1 month ago
3
Make test and make openlane fail

#2122 ssooffiiaannee closed 6 hours ago
12
Generating the PDN fails at the "Hierarchical chip design (with macros)" tutorial

#2121 kietuan opened 1 month ago
0
Clock Network Delay is 0.0 in timing reports after CTS

#2120 Jaswanth-Pappula opened 2 months ago
2
Update PDK

#2119 donn closed 2 months ago
0
Update OpenROAD

#2118 donn closed 2 months ago
0
Enable rtl_macro_placer feature

#2117 vijayank88 opened 2 months ago
0
Automatic macro placement fails to complete PDN stage

#2116 vijayank88 closed 2 months ago
2
Migrate Build System to Match OpenLane 2

#2115 donn closed 1 month ago
0
docker/*/Dockerfile has .gitignore removing yum_dependencies.txt from checkin

#2114 dlmiles closed 2 months ago
2
python3 gui.py --viewer NOT WORKING

#2113 Baungarten-CINVESTAV closed 2 months ago
4
Error in step-17 Running Detailed Routing

#2112 Sanchit-Gupta10 closed 1 day ago
7
Fix Exit Code Propagation When Creating Reproducibles

#2111 donn closed 2 months ago
0
Flow runtime should only have exit status 0 for success when SUCCESS was achieved

#2110 dlmiles closed 2 months ago
0
Fix Clock Port Check

#2109 donn closed 2 months ago
1
Update `libparse`

#2108 donn closed 2 months ago
0
Add python `libparse` dependency to `requirements.txt`

#2107 dlmiles closed 2 months ago
5
Multiple conflicting drivers

#2106 Aadhithya33 closed 2 months ago
4
ldpcEncDec Step 18 18-resizer_design.log failed

#2104 manish03 opened 3 months ago
8
No via inserted -> Unconnected PDN node

#2102 scorbetta opened 3 months ago
3
issues in using the floorplan core utilization command

#2101 Ashutosh-3107 opened 3 months ago
4
Defer compilation of AST of verilog files read in by Yosys till all the files are read

#2100 kareefardi closed 3 months ago
0
Remove SYNTH_READ_BLACKBOX_LIB

#2099 kareefardi closed 3 months ago
0
Wire is used but has no driver

#2098 scorbetta closed 3 months ago
3
Max fanout violation

#2097 MuhammadWamiq003 opened 3 months ago
0
[ERROR PDN-0179] Unable to repair all channels.

#2096 scorbetta closed 3 months ago
4
unable to view the floorplan def files in klayout of oprn lane

#2095 Ashutosh-3107 opened 4 months ago
21
Synthesis warning for out of bounds signal

#2094 scorbetta closed 3 months ago
8
Update OpenROAD

#2093 donn closed 3 months ago
0
OpenLane deleting modules while synthesizing

#2092 Ashutosh-3107 closed 3 months ago
3
the script being called is missing

#2091 nikitaminiaev closed 3 months ago
2
Unbalanced buffer insertion on high fanout designs

#2090 Dolu1990 opened 4 months ago
3
`FP_PIN_ORDER_CFG` not taken into account

#2089 scorbetta closed 4 months ago
5
Using `SYNTH_PARAMETERS` in `config.tcl`

#2087 scorbetta closed 4 months ago
2
PDN unconnected to custom layout(s)

#2086 lrburle closed 4 months ago
30
Fix `-synth_explore` crash

#2085 kareefardi closed 5 months ago
0
Synth explore broken

#2084 kareefardi closed 5 months ago
0
flow succeeds even if clock signal wire is unconnected / doesn't exist

#2083 mattvenn opened 5 months ago
4
Updated link to newer version of spanish docs

#2082 lima-ucr closed 5 months ago
0
Getting -from and -to are no longer supported

#2081 ShankarSNP opened 5 months ago
2
OpenIKLayout DRC report

#2080 kareefardi closed 5 months ago
1
Error in OL Magic GDSII Step - Multi errors on DEF file

#2079 mbaykenar closed 5 months ago
2