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The following 32-bit RISC-V Rust code
```rust
pub unsafe fn allow_ptr(major: usize, minor: usize, slice: *mut u8, len: usize) -> isize {
let res;
asm!("li a0, 3
ecall"
…
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This is going to be a tracker for discussion, questions, feedback, and analyses about the new XXH3 hashes, found in the `xxh3` branch.
@Cyan4973's comments (from `xxhash.h`):
`XXH3` is a new has…
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RISC-V, in order to minimize the number of instructions taking up opcode space, omits certain instructions such as loading an immediate value into a register (since this is the same as adding an immed…
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Issue recognized when writing [[Terminology for instructions that manage microarchitecture state such as caches, prefetchers and predictors]]
We want to have loops to allow [[partial instruction pr…
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Hello @rbertran,
Can you provide some info on how to control the branch taken / not-taken patterns. I see that there is an "InitializeBranchDecorator" pass which deals with T / NT but I'm not sure …
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When trying to compile a Rust file to a .ll.rkt file (.rs -> .ll -> .ll.rkt), the LLVM-Rosette tool throws the following error: “llvm: unknown value: i8* null”.
In the .ll file the only "i8* null"…
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Hello,
We wanted to do verification of the Ariane SoC. For this verification, we need some reference model of the Ariane SoC. Do you have any reference model for the Ariane SoC or reference model o…
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Hi
Our team is considering to use Syntacore SCR-1. Syntacore provided a pre-built toolchain and the version is 7.1.0. However, we compiled a newer version 8.1.0. Recently, we ran the RISC-V complia…
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https://godbolt.org/z/Btr-mt is a very simple naked function that loads a byte. Unfortunately, LLVM chooses not to inline it and turns it into a tail call (because, of course, LLVM is forbidden from p…
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This is an extension to question #6 .
Could you please provide details (or an example) on how to setup a 'model' for a GenericMemoryStreamsPass (implemented at src/microprobe/passes/memory). My un…