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openhwgroup
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cva6
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
https://docs.openhwgroup.org/projects/cva6-user-manual/
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Bump CVV to use improved scoreboard reporting in tandem simulations.
#2301
zchamski
closed
18 hours ago
1
Fix typo on Bitmanip comment
#2300
Gchauvon
closed
18 hours ago
0
update expected area
#2299
cathales
closed
18 hours ago
1
[BUG] Linking error: undefined reference to htif_t::load_payload
#2298
shreyas-kalikar
opened
1 day ago
2
[BUG] `minstret` and `mcycle` do not increment in debug mode, while `dcsr.stopcount` is set to 0 (normal mode)
#2297
xiaoweish
opened
1 day ago
5
CI: Fix riscv-isa-sim builds
#2296
MarioOpenHWGroup
closed
2 days ago
0
Update uvml_mem use for core-v-verif's PR: 2480/2481/2482
#2295
xiaoweish
closed
2 days ago
3
Add vcs -full64 compile option back
#2294
xiaoweish
closed
2 days ago
1
Add interrupt and debug_req uvm agents to UVM TB
#2293
xiaoweish
opened
4 days ago
2
Errors on synthesizing and programming CVA6 on Genesys II
#2292
benlarsendk
opened
4 days ago
0
Bump core/cache_subsystem/hpdcache from `25ffa34` to `27f069b`
#2291
dependabot[bot]
opened
4 days ago
1
Error while running riscv-arch-test
#2290
abhikutari
opened
4 days ago
1
[BUG] stall_instr_fetch signal in core/id_stage.sv will not be driven if CVA6Cfg.RVZCMP is disabled
#2289
ckf104
opened
5 days ago
0
Draft extended hpdcache
#2288
takeshiho0531
opened
6 days ago
9
Makefile : passing the tandem_enable value into UVM testbench
#2287
AyoubJalali
closed
2 days ago
1
[gen_from_riscv_config] add custom-gen.yaml support / fix hyperlinks in csr...
#2286
AbdessamiiOukalrazqou
closed
1 week ago
0
Fix mstatus.mpp in relation to the possible legal values
#2285
JeanRochCoulon
closed
1 week ago
4
Fix WARL behavior of MPP in MSTATUS
#2284
Moschn
closed
1 week ago
0
Fix WARL behavior of MPP
#2283
Moschn
closed
1 week ago
1
decoder.sv: add checks for some B instructions (fix #2276)
#2282
ASintzoff
closed
1 week ago
1
fix lint errors in csr_regfile.sv
#2281
Asmaa-Kassimi
closed
1 week ago
9
[BUG] B extension: incorrect decoding for some instructions in RV32
#2280
ASintzoff
opened
1 week ago
2
Increase max num PMPs to 64
#2279
Moschn
opened
1 week ago
17
superscalar: allow speculative instructions
#2278
cathales
closed
1 week ago
1
[TASK] Implement CVXIF 1.0.0 instruction dedicated to verification
#2277
Gchauvon
opened
1 week ago
0
[BUG] : Decoder Bitmanip instructions
#2276
AyoubJalali
closed
1 week ago
0
Fix the 65x CSR document
#2275
JeanRochCoulon
opened
1 week ago
2
[BUG] : MSTATUS.mpp
#2274
AyoubJalali
closed
1 week ago
7
Use correct fault type for VLSU overflow
#2273
michael-platzer
closed
1 week ago
1
[BUG] LSU overflow (unused vaddr bits unequal) triggers ld/st access fault instead of page fault
#2272
michael-platzer
closed
1 week ago
1
doc: clarify mtval register description when not enabled
#2271
ASintzoff
closed
1 week ago
0
[riscv-config] Update riscv-config tool, CV32A65X specs and the rendering of CSRs.
#2270
zchamski
closed
1 week ago
0
Feat: add add cva6_hpdcache_icache_if_adapter (supports the simplified icache kill mechanism)
#2269
takeshiho0531
closed
1 week ago
6
[BUG] Design doc generation: custom CSRs are missing in the CV32A65X documentation
#2268
zchamski
opened
1 week ago
2
Implement simple uart-based updater for the bootrom
#2267
grg-haas
closed
1 week ago
3
Bump core/cache_subsystem/hpdcache from `32407cb` to `cbdd4f3`
#2266
dependabot[bot]
closed
1 week ago
2
Update submodule core/cache_subsystem/hpdcache
#2265
cfuguet
closed
1 week ago
9
docs: move riscv-isa-manual outside of cv32a65x documentation
#2264
slgth
closed
1 week ago
1
Bump CVV 2465 and adapt cva6pkg
#2263
MarioOpenHWGroup
closed
1 week ago
5
Fix CSR chapter insertion and rename Design Doc names
#2262
JeanRochCoulon
closed
2 weeks ago
1
CSR verification : modify CSR env verif based on new specification
#2261
AyoubJalali
closed
2 weeks ago
1
[Pmp] Parameter for PMP without MMU
#2260
CoralieAllioux
closed
1 week ago
9
[Xcelium flow] Fix initialization of memory array for simulation
#2259
CoralieAllioux
closed
2 weeks ago
1
[gen_from_riscv_config]modify csr updater.py (fix #2191) , modify csr_updater.yaml
#2258
AbdessamiiOukalrazqou
closed
2 weeks ago
0
OBI Agent and assertions integration
#2257
AnouarZajni
closed
2 weeks ago
1
[HOT FIX] fix synthesis
#2256
JeanRochCoulon
closed
2 weeks ago
1
Execute lint job when RTL is modified
#2255
JeanRochCoulon
closed
2 weeks ago
5
add spyglass waiver file to waive ErrorAnalyzeBBox error
#2254
Asmaa-Kassimi
closed
2 weeks ago
2
update riscv-isa-manual to riscv-isa-release-c8c8075-2024-06-12
#2253
ASintzoff
closed
2 weeks ago
2
[BUG] "Virtual" test list fails when icache settings are modified
#2252
LQUA
opened
2 weeks ago
0
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