-
This is a follow-up to #337 . Now that we can generate Verilog from code in standard using memories I have noticed the following issues:
1) In the generated Verilog sometimes the signal "reset" is …
-
I seem to be having an issue when trying to compile the following C file. Below is a working directory with the bambu log file, and I'm using the following version:
Version: PandA 0.9.7-dev - …
-
I've been enjoying cocotb for a few months now. A feature that I think could be helpful would be the ability to perhaps have a python hook to run my tests without invoking the simulator at all.
…
-
## Observed Behavior
When the most significant bit of `mcycleh` is 1, the output value of `Cycles` is a negative value. I feel that the cycle should be treated as an unsigned integer. Is it the expec…
-
Hello
I have a complex system in which, for a module deep in the hierarchy, I can provide a fast C++ model. I would like to simulate the system with Verilator but I'd like to run that particular mo…
-
Compiling the following program produces Verilog with behavior different to the Bluesim simulation.
```bsv
interface Bug;
method ActionValue#(Bool) calculate(Bool change);
endinterface
mo…
-
First, thanks a lot for this great and very powerful Verilog/SV simulator!
We are currently integrating Verilator into DaCe as part of the RTL CodeGen backend (https://github.com/spcl/dace). For th…
-
Hi,
Thanks for this great open source CPU.
After I successfully `make verilog`. I tried `make emu`. But the error occurs, and the error info is as follows.
Thank your very much for any suggest…
jfan0 updated
3 years ago
-
The formal verification tool flags this as a warning (not error). I have attached the MLIR output and a corrected version below.
Warning: Variable(s) is(are) being read asynchronously. This may ca…
-
I would like to use Verilator to perform Single-Event Effect (SEE) fault injection, such as Single-Event Upsets in flip-flops and Single-Event Transients in gates*, to determine a failure rate on a fu…