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OpenXiangShan
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XiangShan
Open-source high-performance RISC-V processor
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rv64v: fix rfWen signal when writing x0 for vector instructions
#3107
Ziyue-Zhang
opened
3 hours ago
0
Backend fix timing
#3106
xiaofeibao-xjtu
opened
6 hours ago
1
Backend: remove loadCancel from dispatch2iq to enqEntry for fix timing
#3105
xiaofeibao-xjtu
opened
6 hours ago
1
refactor: change exception encoding from one-hot to label in order to…
#3104
Yan-Muzi
opened
11 hours ago
1
IFU: cut the number of PC registers
#3103
my-mayfly
opened
21 hours ago
1
bump yunsuan
#3102
sinceforYy
closed
1 day ago
1
rv64v: fix imm read and vtype update after flush pipe
#3101
Ziyue-Zhang
closed
1 day ago
1
VFALU: fix vfredunction fflags
#3100
lewislzh
closed
1 day ago
1
VLSU: Fix vector exception handling and fix bug for SegmentUnit.
#3099
Anzooooo
closed
11 hours ago
3
Update Snapshot.scala
#3098
Jeremy-Jia
opened
2 days ago
0
bump coupledL2
#3097
Tang-Haojin
closed
2 days ago
1
PTW, RVH: fix the bug that the last second stage translation continues after the first stage translation raises af
#3096
pxk27
closed
2 days ago
1
package: change hypervior load's fuOpType
#3095
weidingliu
closed
5 days ago
1
Fix timing of memblock
#3094
good-circle
opened
6 days ago
1
MMU: test refactor page table walker level
#3093
good-circle
opened
6 days ago
1
bpu: disable ittage when no indirect branch & ittage backward shift
#3092
sleep-zzz
opened
6 days ago
2
rv64v: fix some vector bugs in uop split and handle illegal vector instruction
#3091
Ziyue-Zhang
closed
5 days ago
3
StoreQueue: sq entries with exception can deq without allvalid
#3090
good-circle
closed
6 days ago
1
Og2ForVector: fix ImmInfo of vector Exus, it should delay 1 cycle in og2
#3089
sinsanction
closed
6 days ago
1
Entries: optimize timing of mem IQs' response signals
#3088
sinsanction
closed
6 days ago
1
diff: add AlwaysBasicDiff on load event
#3087
xiaokamikami
closed
2 days ago
1
fix: multiple load replays lead to running out of FTQ entries
#3086
Yan-Muzi
closed
6 days ago
1
Backend: fix Uncertain Layency Fu's clock gate
#3085
sinceforYy
closed
6 days ago
1
In VCS simulation, multi-core simulation of some harts ended prematurely due to incorrect execution of SEQZ instruction
#3084
meiqin0
opened
1 week ago
1
BypassNetwork: ExuOH->ExuVec, add mask for forwardOrBypassValidVec3
#3083
xiaofeibao-xjtu
closed
1 week ago
1
VLSU: fix bug related to new VLSU
#3082
Anzooooo
closed
1 week ago
2
ci: use PGO for nightly regression
#3081
cyyself
closed
1 week ago
1
CI: enable PGO when building emu for CI
#3080
cyyself
closed
1 week ago
1
ICache: Init registers to prevent x-state
#3079
ngc7331
closed
1 week ago
0
HPTW, RVH: fix the bug that non-leaf and level >= 2 pte doesn't raise pagefault.
#3078
pxk27
closed
1 week ago
6
PageTableCache, RVH: fix the error fence when sfence_vma or hfence_gvma is executed
#3077
pxk27
closed
1 week ago
1
DCache: Fix x-prop caused by l2_error
#3075
bosscharlie
closed
1 week ago
2
ci: use 16 threads for emu-basics
#3074
Tang-Haojin
closed
1 week ago
1
vl: remove vl from CSR, assign it to vl which store in regfiles
#3073
Ziyue-Zhang
closed
1 week ago
2
make verilog NUM_CORES=4 gets error
#3072
meiqin0
opened
1 week ago
7
ci: add simple xprop test through vcs
#3071
Tang-Haojin
closed
1 week ago
4
MISC: Update CODEOWNERS about ICache
#3070
cebarobot
closed
1 week ago
0
MISC: turn to use issue form to avoid improper filling
#3069
cebarobot
closed
1 week ago
0
StoreQueue: fix X when write StoreBuffer
#3068
weidingliu
closed
1 week ago
1
ci: do not run ci if only images are changed
#3067
Tang-Haojin
closed
1 week ago
0
VirtualLoadQueue: remove useless logic
#3066
good-circle
closed
1 week ago
1
VPU: fix vfreduction bug; remove redundant logic for scalar compute
#3065
lewislzh
closed
1 week ago
1
MISC: skip CI for commits that do not modify core sources.
#3064
cebarobot
closed
1 week ago
3
DCache: Move L2 refill error signal to refill_info
#3063
bosscharlie
closed
1 week ago
1
Fix timing of memblock
#3062
good-circle
closed
1 week ago
4
Add format checking for XiangShan
#3061
Yan-Muzi
opened
2 weeks ago
3
IssueQueue: when src0-2 read vector reg #0, transfer to src3 to read v0
#3060
sinsanction
closed
1 week ago
1
MMU: LLPTW should report PF when pte is not leaf
#3059
good-circle
closed
2 weeks ago
1
vset: fix old vl read for vsetvl and vsetvli instructions
#3058
Ziyue-Zhang
closed
1 week ago
1
Assertion failed at UserYanker.scala:63 assert (!out.r.valid || r_valid) // Q must be ready faster than the response
#3057
Jeremy-Jia
opened
2 weeks ago
1
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