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OpenXiangShan
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XiangShan
Open-source high-performance RISC-V processor
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MISC: Update CODEOWNERS about ICache
#3070
cebarobot
closed
2 weeks ago
0
MISC: turn to use issue form to avoid improper filling
#3069
cebarobot
closed
2 weeks ago
0
StoreQueue: fix X when write StoreBuffer
#3068
weidingliu
closed
2 weeks ago
1
ci: do not run ci if only images are changed
#3067
Tang-Haojin
closed
2 weeks ago
0
VirtualLoadQueue: remove useless logic
#3066
good-circle
closed
2 weeks ago
1
VPU: fix vfreduction bug; remove redundant logic for scalar compute
#3065
lewislzh
closed
2 weeks ago
1
MISC: skip CI for commits that do not modify core sources.
#3064
cebarobot
closed
2 weeks ago
3
DCache: Move L2 refill error signal to refill_info
#3063
bosscharlie
closed
2 weeks ago
1
Fix timing of memblock
#3062
good-circle
closed
1 week ago
4
Add format checking for XiangShan
#3061
Yan-Muzi
opened
2 weeks ago
3
IssueQueue: when src0-2 read vector reg #0, transfer to src3 to read v0
#3060
sinsanction
closed
2 weeks ago
1
MMU: LLPTW should report PF when pte is not leaf
#3059
good-circle
closed
2 weeks ago
1
vset: fix old vl read for vsetvl and vsetvli instructions
#3058
Ziyue-Zhang
closed
2 weeks ago
1
Assertion failed at UserYanker.scala:63 assert (!out.r.valid || r_valid) // Q must be ready faster than the response
#3057
Jeremy-Jia
opened
2 weeks ago
1
vfalu: Use oldVd as input to mgu in last Uop for vfred inst
#3056
sinceforYy
closed
2 weeks ago
1
Revert "LSQ: optimize static clock gating coverage (#3023)"
#3055
Tang-Haojin
closed
2 weeks ago
1
Timing optimization for MemScheduler
#3054
sinsanction
closed
2 weeks ago
1
VPU: new vcompress to fit v0&vl split; fix vfredsum/min/max
#3053
lewislzh
closed
2 weeks ago
1
Backend fixtiming
#3052
xiaofeibao-xjtu
closed
2 weeks ago
1
Frontend new ICache
#3051
ssszwic
closed
23 hours ago
5
Update CODEOWNERS about ICache
#3050
ssszwic
closed
2 weeks ago
0
ci: use faster bbl-based SMP linux 4.18.0
#3049
Tang-Haojin
closed
2 weeks ago
1
LSQ: refactor vector load/store commit judging logic to fix X in vcs
#3048
weidingliu
closed
2 weeks ago
1
bump yunsuan : Fpu,fsqrt: fix error when computing square roots for powers of 2 and sNan qNan error
#3047
lewislzh
closed
3 weeks ago
1
LSQ: use RegNextWithEnable when RegEnable.next contains RegEnable.enable
#3046
huxuan0307
closed
3 weeks ago
1
PTW, LLPTW: change the flush signal to be same to the flush in L2TLB
#3045
pxk27
closed
3 weeks ago
2
L1CacheErrorInfo: code refactor for correct and convenient clockgate
#3044
Maxpicca-Li
closed
2 weeks ago
1
MainPipe: set `full_overwrite` when each byte in store is masked
#3043
linjuanZ
closed
3 weeks ago
1
CoupledL2, Uncache, LSQ: support non-data error handling
#3042
linjuanZ
closed
3 weeks ago
1
StoreQueue: fix bug after refactor commit logic
#3041
weidingliu
closed
3 weeks ago
1
v0 vl split
#3040
xiaofeibao-xjtu
closed
2 weeks ago
1
vtype: fix bug when vsetvl instruction's rd and rs1 are x0
#3039
Ziyue-Zhang
closed
3 weeks ago
1
IFU: fix the bug of postponing MMIO instruction fetch strategy
#3038
my-mayfly
closed
1 week ago
2
Exception: hasException assign in rename, add illegalInstr and virtualInstr
#3037
xiaofeibao-xjtu
closed
3 weeks ago
1
prefetch: fix misalign of the control signal for prefetch pc
#3036
Maxpicca-Li
closed
3 weeks ago
1
FPU: fix f2v boxing error when higher bits are not all zeros
#3035
lewislzh
closed
3 weeks ago
1
VLSU: fix bug of vector load/store split & support for segment instruction exception
#3033
weidingliu
closed
3 weeks ago
2
Backend fixtiming: fix rab/exuwb/wbtorob timing
#3032
lewislzh
closed
2 weeks ago
2
clockgate: set default initialization with 0 to fix X in vcs
#3031
Maxpicca-Li
closed
3 weeks ago
1
misc: fix compile error on mill 0.11.7
#3030
eastonman
closed
3 weeks ago
2
config: use smaller BPU in MinimalConfig
#3029
eastonman
closed
3 weeks ago
1
deps: bump chisel and scala
#3028
eastonman
closed
3 weeks ago
8
bpu: use (27, 12, 12) segmented PC in BPU
#3027
eastonman
opened
3 weeks ago
1
difftest: check load only when isAmo or isLoad and skip MMIO
#3026
klin02
closed
3 weeks ago
2
LLPTW: fix error state transition when the new llptw req is onlyStage1
#3025
pxk27
closed
3 weeks ago
1
Update CODEOWNERS
#3024
chenguokai
closed
4 weeks ago
3
LSQ: optimize static clock gating coverage
#3023
jin120811
closed
4 weeks ago
1
coupledL2, L2Top, XSTile: refactor CoupledL2 top-level framework
#3022
linjuanZ
closed
4 weeks ago
1
VFMA,VFDivSqrt: fix bug of fflagsEn
#3021
xiaofeibao-xjtu
closed
1 month ago
1
StoreQueue: Commit storequeue entry by judging robidx
#3020
good-circle
closed
3 weeks ago
1
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