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Hello team,
I encountered one error when running `renode litex-vexriscv-tflite.resc` on one [TF Lite micro project](https://github.com/antmicro/litex-vexriscv-tensorflow-lite-demo). The error is:
…
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The current `setup.py` does not list any dependencies but litex-boards does depend on migen, litex and a bunch of litex modules.
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Hi,
I try to build zephyr on vexriscv using litex-buildenv on Ubuntu 20.04:
```
$ gti clone https://github.com/timvideos/litex-buildenv
$ export CPU=vexriscv
$ export CPU_VARIANT=full
$ expo…
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Dear @btashton,
What are the IP cores should be added in Zybo Z7 platform which is already written in litex-boards( https://github.com/litex-hub/litex-boards)
Does generating the bitstream with…
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Hi @jevinskie
Thank you for this work.
I had tried with deca board as
```sh
./deca.py --build
````
but the build with Quartus (lite, 18.1) failed with messages
```sh
Error (125048): Error rea…
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Hi,
I struggled with this strange issue for a couple of days and finally found out that,
for some weird reason, configuration failed (DONE pin on the FPGA not coming high)
when I tried to load a L…
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On Debian testing with litex-buildenv v0.0.4-592-gf2c790cc36d7. I am configured for CPU=vexriscv PLATFORM=arty TARGET=net and am running download-env.sh for the first time:
```
Installing hexfile …
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I'm trying to observe the signal while running the litex_sim using vexriscv. v file. That work well, I can see all my dumped signals in the sim.vcd file with gtkwave.
But I have a problem for the t…
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I am trying to figure out how to build.
Summary:
I'll update the docs but I need info: is the wiki page I started the best we have, or is there something I missed?
Details:
https://hdmi2…
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Testing MiSTeR Template core with LiteX-Sim will allow doing a first code portability test with Verilator and will also be useful to create a first simulation environment test.