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This is not trivial to implement for the plethora of cores already on the list, but a good suggestion.
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when I run this command , it gets some errors. make clean simulate verify postverify XLEN=32 RISCV_DEVICE=I
It shows 'src/JALR-01.S:31: Error: unrecognized opcode `csrw mepc,t0', extension `zicsr' re…
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Changes
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- 2021/06/03
- Add an new option d.
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The ISA spec has specify the ISA extension could be describe the arch string, and toolchain are using this way to control the code gen, and …
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The following does not error or warn:
```
$ ./bin/clang /tmp/test.c -target riscv64 -march=rv32i -o - -S
```
And it produces code according to the value of `-march`:
```
.text
.…
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The imperasISACOV code appears to have a read after write bug that reads the new value rather than the old when a source is also used as a destination register.
For example, rv32i add misses a few …
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I prepared a new release for the xPack GNU RISC-V Embedded GCC, which now uses the upstream sources instead of the SiFive repos.
The toolchain seems functional, it remains to be seen how compatible…
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CORE-V-XIF needs to define how XIF can be used together with RV32E.
An initial proposal:
- A processor configured to use RV32E will declare all instructions that would use a source or destinatio…
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Following analysis of the architectural coverage from RISC-DV there are a few small issues to investigate
- [ ] rv32i_misc_cg - Instructions in this group are getting executed but aren't appearing …
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Could you add a method to add syscalls to the CPU? Thanks!
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--with-abi=ilp32 is not supported for ISA rv64imafdc
make[1]: *** [Makefile:4549: configure-gcc] Error 1
make[1]: Leaving directory '/Projects/marmik_project/shubhangi.verma/spu32/riscv-gcccd/riscv-…