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AntonLydike
/
riscemu
RISC-V emulator in python
MIT License
48
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13
forks
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floats: Add fcvt instructions for doubles, and fix their overflow behaviour to reflect the spec
#53
AntonLydike
closed
4 months ago
0
Allow register indices in addition to ABI names
#52
superenginegit
closed
9 months ago
1
Allow addressing Registers by their number (e.g. x0)
#51
superenginegit
closed
9 months ago
9
Snitch frep extension support
#50
AntonLydike
closed
11 months ago
0
Add support for flen=64
#49
AntonLydike
closed
11 months ago
1
Feature m instruction set
#48
Joshy-R
closed
4 months ago
6
Big cleanup work
#47
AntonLydike
closed
11 months ago
0
Add p2align assembler directive
#46
AntonLydike
closed
11 months ago
0
Fix typos
#45
kianmeng
closed
11 months ago
3
Add support for source maps
#44
AntonLydike
opened
1 year ago
0
Added streaming register bank and basic xssr instructions
#43
KGrykiel
closed
1 year ago
3
Allow reading from stdin
#42
AntonLydike
closed
1 year ago
0
Support the snitch extension
#41
AntonLydike
opened
1 year ago
0
Move to explicit handling of immediate values
#40
AntonLydike
closed
1 year ago
1
Move to poetry for development
#39
AntonLydike
closed
1 year ago
1
fcvt instructions convert values, not bits
#38
superlopuh
closed
1 year ago
1
Immediate Rework
#37
KGrykiel
closed
1 year ago
0
Inconsistency with RV32F
#36
kingiler
opened
1 year ago
9
Fix jump instruction with relative offset
#35
kingiler
closed
1 year ago
1
changed = to +=
#34
KGrykiel
closed
1 year ago
6
j and jal fix
#33
KGrykiel
closed
1 year ago
1
Debugger fix
#32
KGrykiel
closed
1 year ago
2
allow for infinite registers in sw/lw instructions
#31
superlopuh
closed
1 year ago
0
[WIP] wip tokenizer.parse_arg reorders arguments incorrectly for sw instrction
#30
superlopuh
closed
4 months ago
1
j and jal instructions jump to absolute offset when immediate is int
#29
superlopuh
closed
11 months ago
1
Fix formatting issues for CI
#28
adutilleul
closed
1 year ago
0
Fix some issues in the RV32F extension implementation
#27
adutilleul
closed
1 year ago
3
Move CSR from priv to non-priv CPU
#26
AntonLydike
closed
11 months ago
1
Make `RiscemuMain` support custom syscall extensions
#25
AntonLydike
opened
1 year ago
0
Make `RiscemuMain` support non-file inputs
#24
AntonLydike
opened
1 year ago
0
Allow for capturing the output
#23
AntonLydike
opened
1 year ago
0
Add support for floats
#22
AntonLydike
closed
1 year ago
1
add py.typed file for riscemu to declare itself as a typed python package
#21
superlopuh
closed
1 year ago
0
add some typing annotations
#20
superlopuh
closed
1 year ago
0
WIP: Float support
#19
AntonLydike
closed
1 year ago
0
Deploy RiscEmu in a JupyterLite distribution.
#18
PapyChacal
closed
1 year ago
1
Ready RISCEMU for pyodide
#17
AntonLydike
closed
1 year ago
1
Fix sign issue in parse_rd_rs_rs
#16
K-W-Li
closed
1 year ago
1
Method to add syscalls?
#15
RobertBaruch
opened
2 years ago
5
Disable output "[CPU] Program exited with code 0"
#14
tobiasgrosser
closed
1 year ago
1
Requirement to have .text section
#13
tobiasgrosser
closed
2 years ago
2
Setting exit code via sys.exit(CODE)
#12
tobiasgrosser
closed
2 years ago
1
Integer wrapping incorrect for large numbers
#11
tobiasgrosser
closed
2 years ago
2
Data OPs not working as intended
#10
niklasr22
closed
2 years ago
0
[priv] triggering a timer interrupt directly after returning from kernel decrements the PC by 4
#9
AntonLydike
opened
2 years ago
0
Support for pseudoops
#8
tobiasgrosser
opened
2 years ago
3
LH and LB instructions don't sign-extend loaded values
#7
niklasr22
closed
2 years ago
1
RuntimeError("No write pls")
#6
tobiasgrosser
closed
2 years ago
2
tokenizer reimplemented
#5
AntonLydike
closed
2 years ago
0
Register overflow is not implemented
#4
tobiasgrosser
closed
2 years ago
1
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