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Hello,
Nova v3.10.0 introduce a new standalone action for running actions without selecting resources. which make a good use case to import data to your resource without using this package.
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I want to create a simple logical netlist, which contains a flip-flop like FDCE and VCC/GND sources based on RapidWright in python. Then, I want to place this simple circuit in a single site.
More s…
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A receita federal mudou completamente o layout dos arquivos e tambem a pagina de download.
O novo link: https://www.gov.br/receitafederal/pt-br/assuntos/orientacao-tributaria/cadastros/consultas/dado…
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Hello, I'm new to the program and I'm trying to analyze some fastq files I jusr received. Reads are already demultiplexed, so I put them in the 2_Demultiplexing folder. Whenever I try to merge PE read…
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From https://gist.github.com/regymm/3cfaefb1cc5922d72a8d1ccc775efddf
```
1. Executing Verilog-2005 frontend: ../cache_cpu.v
Parsing Verilog input from `../cache_cpu.v' to AST representation.
Gener…
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I am not able to export a .xml.
I have the following error.
Can anyone help me?
![error](https://github.com/mitsuba-renderer/mitsuba-blender/assets/71104353/c18a257b-98f9-4233-a73b-0f249a89ae25)
!…
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Hi,
I got the following output when reading the attached design checkpoint
>==============================================================================
== Reading DCP: soc…
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My code is as follows.
```java
public static void main(String[] args) throws FileNotFoundException {
Design design = Design.readCheckpoint("socket_cc.dcp", "socket_cc.edf");
EDIFNetlist …
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I have attached some sample code/dcp to reproduce this error. I am using Vivado 2023.1
[bad_port_py.txt](https://github.com/Xilinx/RapidWright/files/12015546/bad_port_py.txt)
[design.zip](https://…
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May be related to #21 .
Using the base files for both Lucid and Verilog projects, `Build Project` fails:
```
Starting iceCube2...
C:\Program Files\Alchitry\Alchitry Labs>SET TCL_LIBRARY=C:\…