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This is to track all the things that need to be changed when 3.7 is deprecated:
- [ ] Change ast.Num to ast.Constant
> Deprecated since version 3.8: Old classes ast.Num, ast.Str, ast.Bytes, ast.…
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1. Have a browse to button for the executable/image file
2. Convert Windows path delimiters to '/' or double escape them. Make it much easier to paste a path from Windows Explorer.
3. Have a mechani…
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Hello,
because I was not able to find project like your's I have written my [own](https://github.com/Nic30/pyMathBitPrecise).
I added reference on your project to similar project in readme section…
Nic30 updated
5 years ago
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It appears that the current code to generate VCD trace files has hardcoded the value '1ns' as the timescale. Would be good to also support '1ps' timescales.
I have added a feature to allow the user…
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# [enhancement] limited top-level list-of-signal port conversion
Currently, list-of-signals in the top-level is not supported for conversion. This issue/enhancement proposes that a subset of a list-…
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A simple enhancement request. I think in line with the idea of Rust design to give low level control, to offer an ergonomic API that reduces the chances for bugs while keeping code efficient, and at t…
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There is one bigger and two minor thingies here but idk if creating 3 separate issues is a good thing in this case.
So I'm implementing DDR mode where data is sent on both clock edges. Unfortunatel…
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Always_comb will except when an internal signal is used both as in and out in the same process, even though this is entirely valid in VHDL. (No idea about Verilog)
The workaround I have used is to …
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When creating re-usable modules we create output signals, which quite often are not all used in an instantiation, and cause **undesirable warnings**.
In VHDL we have the _open_ keyword to tell the com…
josyb updated
8 years ago
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Xilinx newbie, but I ran source build_all.tcl and ended up with
```
Xilinx/Vivado_HLS/2016.1/include/etc/ap_int_sim.h:75:10: fatal error: 'stdio.h' file not found
#include
^
1 error…