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Any special reason why there is no Verilator test bench for the 'vscale-generic' system, as there is for the 'or1200-generic' system (or1200-generic/bench/verilator/tb.cpp)?
Is there a way to simul…
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While going through the X-HEEP ASIC flow I can't seem to run the openroad-sky130 target and get GDS out.
I have OpenROAD installed globally on my machine, oss cad suite and I've ran the installation…
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(follow up https://github.com/agurfinkel/btor2mlir/issues/40)
I ran the below steps (using the commands from [`get_cex_seahorn.sh`](https://github.com/jetafese/btor2mlir/blob/345625097142e221be4c3a…
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Since the MISRA-C runtime has been merged in PR #3934 and discussed in RFC #3159 , I think now it's time to migrate uTVM standalone runtime ( introduced in PR #3567 )
### Rationale
* MISRA-C ru…
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Hi Lawrie and thanks for that great work!
As you mentioned:
> This implementation has been done from the specification, without access to any Raspberry Pi HDL. It is currently incomplete, but so…
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Building code with riscv32imc toolchain, the code is stucking in simulation cxxdemo and it is not stucking when built with the riscv32ic toolchain. Looks like there is some problem with the PCPI/Multi…
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Hello. I'd like to use Alacritty inside a Rust EGUI project. To accomplish this, I'm thinking I'll use a monospace text field in EGUI with text cell changes I get from Alacritty. At a high level, wher…
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hello!
I'm having a problem implementing the core in vivado.
I have installed the riscv gnu toolchain and I am sure that it works ok, I modified the Makefile ($TOOLCHAINPREFIX).
I ran the makfil…
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How to repeat:
1. Run ```$ placement_tool=graywolf qflow gui```
2. Choose ```Technology=osu035```
3. Choose the Verilog file ```map9v3.v```
4. Hit ```Run``` for Preparation, then for Synthesis
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The PMOD outputs will need to be re-arranged to avoid using the high speed differential outputs as single-ended outputs since this can cause significant crosstalk:
https://github.com/AdamMooers/ups…