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This is to keep track of this issue: https://github.com/efabless/openlane/issues/26, where @harikumar27399 is hardening a relatively large design. Magic takes forever and then crashes on a machine wit…
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### Subject
[Flow] for any util, flow Makefile, or flow script issues.
### Describe the bug
results/sky130hd/gcd/base/6_1_merged.gds only contains pin geometry, it's missing the net geometry for de…
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The first publication of this is missing files required for optimal Cadence Virtuoso usage. These files will be released publically at a future date after further work.
These files are;
* OpenAcc…
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Similar to how there is a script which combines the timing data into a single large liberty file. We need a script which does the same for the LEF files.
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1. Is there a community to assists with questions? Can you provide a link?
2. Is there a tutorial on how to start analog simulation with ngspice?
(Also just a basic inverter would be enough to get t…
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The first publication of this PDK is missing files required to do design verification with Mentor Calibre. Scripts for generating these files from the published documentation will be released at a fut…
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Antenna repair wants to insert large numbers of antenna diodes on some of the nets in Microwatt. The issue is at its worst when large met4 wires feed a minimum size gate (eg a 1x strength sky130hd cel…
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Hi ,
Running DRC for sky130_fd_pr_reram__reram_cell.gds file , getting below DRC :
m2.5 [sky130_fd_pr_reram__reram_cell]
m2.5 : min. m2 enclosure of via of 2 opposite edges : 0.085um
polygon…
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## Expected Behavior
Tap cells LEF version 5.5 should have CLASS CORE.
WELLTAP statement is for version 5.6 and later but the LEF file says version 5.5.
## Actual Behavior
The LEF (version 5.…
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If the intent was to follow the standard used by the sky130 PDK, then this is an epic fail. It needs correcting on multiple fronts.
For starters, the standard cell verilog modules make references …