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Hi all,
Does anyone encounter the same error as below?
Thanks
```shell
❯ pytest
========================================================================== test session starts ==================…
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```
import magma as m
class Foo(m.Circuit):
IO = ["I", m.In(m.Bit), "O", m.Out(m.Bit)]
@classmethod
def definition(io):
anon = m.Bit()
#m.wire(anon, io.I) …
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http://www.swig.org/
Could allow us to automatically generate Python and Lua bindings
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I've been thinking about the whole model/driver/monitor, transaction level modeling stuff. The high level idea is that a model has high-level functions, a driver lowers these functions to circuit inpu…
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```
Value = Const()
| Var(string name)
| Arg(string name)
| Op(Value*)
attribute(ValueType)
Stmt = Assign(string varname, Value)
| Return(Value)
TypeGen(Params…
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While we're migrating `mantle` into the core, we have an opportunity to revisit our design for the FPGA specific mantle targets.
# Primitives
Magma/mantle offer a set of primitives that can be use…
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There's been requests for support for passing named temporary values down through the toolchain. For now, we could add support for named values such as `x = Bit(name="x")` and find a way to pass that…
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So I have the following magma code:
```python
import magma as m
class Foo(m.Circuit):
io = m.IO(I=m.In(m.Bits[8]), O=m.Out(m.Bits[8]))
tmp = io.I + 42
io.O @= tmp
m.comp…
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When I did an exhaustive test on floating points, I noticed performance issue with fault generated testbench. The test vectors size is 0x500 * 0x500 = 0x190000 ~ 1 million data points. Here is the pro…
Kuree updated
3 years ago
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Basic idea is to create something low-level, like LLVM Bitcode or WebAssembly, to create the HDL compilers emit the code in this format, which will be fed to the routers/synthesizers after. This will …